Issued Patents All Time
Showing 101–125 of 128 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9853630 | Skew-tolerant flip-flop | Chi-Lin Liu, Lee-Chung Lu, Shang-Chih Hsieh, Bor-Tyng Lin | 2017-12-26 |
| 9641161 | Flip-flop with delineated layout for reduced footprint | Chi-Lin Liu, Ting-Wei Chiang, Hui-Zhong Zhuang, Lee-Chung Lu, Shang-Chih Hsieh +1 more | 2017-05-02 |
| 9564896 | Post-silicon tuning in voltage control of semiconductor integrated circuits | Chien-Ju Chao, Chin-Shen Lin, Nitesh Katta, Kuo-Nan Yang, Chung-Hsing Wang | 2017-02-07 |
| 9509301 | Voltage control of semiconductor integrated circuits | Chien-Ju Chao, Chou-Kun Lin, Chin-Shen Lin, King-Ho Tam, Kuo-Nan Yang +1 more | 2016-11-29 |
| 9501602 | Electromigration-aware layout generation | Nitesh Katta, Chin-Shen Lin, Yi-Chuin Tsai, Chou-Kun Lin, Kuo-Nan Yang +1 more | 2016-11-22 |
| 9405883 | Power rail for preventing DC electromigration | Chin-Shen Lin, Nitesh Katta, Chou-Kun Lin, Yi-Chuin Tsai, Chi-Yeh Yu +1 more | 2016-08-02 |
| 9367660 | Electromigration-aware layout generation | Nitesh Katta, Chin-Shen Lin, Yi-Chuin Tsai, Chien-Ju Chao, Kuo-Nan Yang +1 more | 2016-06-14 |
| 9311440 | System and method of electromigration avoidance for automatic place-and-route | King-Ho Tam, Meng-Xiang Lee, Li-Chung Hsu, Chi-Yeh Yu, Chung-Min Fu +1 more | 2016-04-12 |
| 9262573 | Cell having shifted boundary and boundary-shift scheme | Kuo-Nan Yang, Chou-Kun Lin, Yi-Chuin Tsai, Chien-Ju Chao, Chung-Hsing Wang | 2016-02-16 |
| 9201107 | Cell characterization with Miller capacitance | Nitesh Katta, King-Ho Tam, Kuo-Nan Yang, Chung-Hsing Wang | 2015-12-01 |
| 9171926 | Channel doping extension beyond cell boundaries | Kuo-Nan Yang, Chou-Kun Lin, Yi-Chuin Tsai, Chien-Ju Chao, Chung-Hsing Wang | 2015-10-27 |
| 9165882 | Power rail for preventing DC electromigration | Chin-Shen Lin, Nitesh Katta, Chou-Kun Lin, Yi-Chuin Tsai, Chi-Yeh Yu +1 more | 2015-10-20 |
| 9152751 | Metal lines for preventing AC electromigration | Chin-Shen Lin, Nitesh Katta, Chou-Kun Lin, Yi-Chuin Tsai, Chien-Ju Chao +1 more | 2015-10-06 |
| 9047433 | Cell and macro placement on fin grid | Kuo-Nan Yang, Chou-Kun Lin, Yi-Chuin Tsai, Chien-Ju Chao, Chung-Hsing Wang | 2015-06-02 |
| 8937358 | Channel doping extension beyond cell boundaries | Kuo-Nan Yang, Chou-Kun Lin, Yi-Chuin Tsai, Chien-Ju Chao, Chung-Hsing Wang | 2015-01-20 |
| 8847284 | Integrated circuit with standard cells | Kuo-Nan Yang, Chou-Kun Lin, Yi-Chuin Tsai, Chien-Ju Chao, Chung-Hsing Wang | 2014-09-30 |
| 8499274 | Computer implemented system and method for leakage calculation | Chien-Ju Chao, King-Ho Tam, Chung-Hsing Wang, Huan Chi Tseng | 2013-07-30 |
| 8289063 | Clock distribution network architecture with clock skew management | Juang-Ying Chueh, Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler | 2012-10-16 |
| 7956664 | Clock distribution network architecture with clock skew management | Juang-Ying Chueh, Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler | 2011-06-07 |
| 7880507 | Circular edge detector | Jente B. Kuang, Alan J. Drake, Gary Dale Carpenter, Fadi H. Gebara | 2011-02-01 |
| 7760565 | Wordline-to-bitline output timing ring oscillator circuit for evaluating storage array performance | Jente B. Kuang, Hung C. Ngo, Kevin John Nowka, Liang Pang, Jayakumaran Sivagnaname | 2010-07-20 |
| 7759980 | Circular edge detector for measuring timing of data signals | Jente B. Kuang, Alan J. Drake, Gary Dale Carpenter, Fadi H. Gebara | 2010-07-20 |
| 7719317 | Clock distribution network architecture with resonant clock gating | Juang-Ying Chueh, Visvesh S. Sathe, Marios C. Papaefthymiou | 2010-05-18 |
| 7719316 | Clock distribution network architecture for resonant-clocked systems | Juang-Ying Chueh, Visvesh S. Sathe, Marios C. Papaefthymiou | 2010-05-18 |
| 7668037 | Storage array including a local clock buffer with programmable timing | Gary Dale Carpenter, Fadi H. Gebara, Jente B. Kuang, Kevin John Nowka, Liang Pang | 2010-02-23 |