Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9041451 | Resonant clock distribution network architecture for tracking parameter variations in conventional clock distribution networks | Alexander Ishii | 2015-05-26 |
| 8659338 | Resonant clock distribution network architecture with programmable drivers | Alexander Ishii | 2014-02-25 |
| 8593183 | Architecture for controlling clock characteristics | Alexander Ishii | 2013-11-26 |
| 8502569 | Architecture for operating resonant clock network in conventional mode | Alexander Ishii | 2013-08-06 |
| 8461873 | Resonant clock and interconnect architecture for digital devices with multiple clock networks | Alexander Ishii | 2013-06-11 |
| 8400192 | Architecture for frequency-scaled operation in resonant clock distribution networks | Alexander Ishii | 2013-03-19 |
| 8368450 | Architecture for adjusting natural frequency in resonant clock distribution networks | Alexander Ishii | 2013-02-05 |
| 8362811 | Architecture for single-stepping in resonant clock distribution networks | Alexander Ishii | 2013-01-29 |
| 8358163 | Resonant clock distribution network architecture for tracking parameter variations in conventional clock distribution networks | Alexander Ishii | 2013-01-22 |
| 8339209 | Method for selecting natural frequency in resonant clock distribution networks with no inductor overhead | Alexander Ishii | 2012-12-25 |
| 8289063 | Clock distribution network architecture with clock skew management | Juang-Ying Chueh, Jerry Chang Jui Kao, Visvesh S. Sathe, Conrad H. Ziesler | 2012-10-16 |
| 7973565 | Resonant clock and interconnect architecture for digital devices with multiple clock networks | Alexander Ishii | 2011-07-05 |
| 7956664 | Clock distribution network architecture with clock skew management | Juang-Ying Chueh, Jerry Chang Jui Kao, Visvesh S. Sathe, Conrad H. Ziesler | 2011-06-07 |
| 7719316 | Clock distribution network architecture for resonant-clocked systems | Juang-Ying Chueh, Jerry Chang Jui Kao, Visvesh S. Sathe | 2010-05-18 |
| 7719317 | Clock distribution network architecture with resonant clock gating | Juang-Ying Chueh, Jerry Chang Jui Kao, Visvesh S. Sathe | 2010-05-18 |
| 7622977 | Ramped clock digital storage control | Conrad H. Ziesler | 2009-11-24 |
| 7355454 | Energy recovery boost logic | Visvesh S. Sathe, Conrad H. Ziesler | 2008-04-08 |
| 6879190 | Low-power driver with energy recovery | Joohee Kim | 2005-04-12 |
| 6777992 | Low-power CMOS flip-flop | Conrad H. Ziesler | 2004-08-17 |
| 6742132 | Method and apparatus for generating a clock signal having a driven oscillator circuit formed with energy storage characteristics of a memory storage device | Conrad H. Ziesler | 2004-05-25 |