AI

Alexander Ishii

CS Cyclos Semiconductor: 11 patents #1 of 2Top 50%
NE Nec: 4 patents #14 of 91Top 20%
NV NVIDIA: 3 patents #2,112 of 7,811Top 30%
NI Nec Research Institute: 1 patents #57 of 127Top 45%
Overall (All Time): #231,935 of 4,157,543Top 6%
19
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11882678 Redundant isolation of rack manifolds for datacenter cooling systems Harold Miyamura, Jeremy Rodriguez, Alex R. Naderi, Ali Heydari 2024-01-23
11327900 Securing memory accesses in a virtualized environment Samuel H. Duncan, Sanjeev Kumar Jain, Mark Hummel, Vyas Venkataraman, Olivier Giroux +3 more 2022-05-10
10769076 Distributed address translation in a multi-node interconnect fabric Samuel H. Duncan, Sanjeev Kumar Jain, Mark Hummel, Vyas Venkataraman, Olivier Giroux +3 more 2020-09-08
9041451 Resonant clock distribution network architecture for tracking parameter variations in conventional clock distribution networks Marios C. Papaefthymiou 2015-05-26
8659338 Resonant clock distribution network architecture with programmable drivers Marios C. Papaefthymiou 2014-02-25
8593183 Architecture for controlling clock characteristics Marios C. Papaefthymiou 2013-11-26
8502569 Architecture for operating resonant clock network in conventional mode Marios C. Papaefthymiou 2013-08-06
8461873 Resonant clock and interconnect architecture for digital devices with multiple clock networks Marios C. Papaefthymiou 2013-06-11
8400192 Architecture for frequency-scaled operation in resonant clock distribution networks Marios C. Papaefthymiou 2013-03-19
8368450 Architecture for adjusting natural frequency in resonant clock distribution networks Marios C. Papaefthymiou 2013-02-05
8362811 Architecture for single-stepping in resonant clock distribution networks Marios C. Papaefthymiou 2013-01-29
8358163 Resonant clock distribution network architecture for tracking parameter variations in conventional clock distribution networks Marios C. Papaefthymiou 2013-01-22
8339209 Method for selecting natural frequency in resonant clock distribution networks with no inductor overhead Marios C. Papaefthymiou 2012-12-25
7973565 Resonant clock and interconnect architecture for digital devices with multiple clock networks Marios C. Papaefthymiou 2011-07-05
6556571 Fast round robin priority port scheduler for high capacity ATM switches Sharif M. Shahrier 2003-04-29
6424622 Optimal buffer management scheme with dynamic queue length thresholds for ATM switches Ruixue Fan, Brian L. Mark, Gopalakrishnan Ramamurthy, Qiang Ren 2002-07-23
6389019 Time-based scheduler architecture and method for ATM networks Ruixue Fan, Brian L. Mark, Gopalakrishan Ramamurthy 2002-05-14
5644499 Retiming gated-clocks and precharged circuit structures — 1997-07-01
5448567 Control architecture for ATM networks Rajiv S. Dighe, Gopalakrishnan Ramamurthy 1995-09-05