Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11017099 | Systems and methods for entropy balanced population measurement | Nicolas Remy, Andrew Smith, Joseph Kelly, James Robert Koehler, Xiaojing Wang | 2021-05-25 |
| 10607254 | Attribution modeling using withheld or near impressions | Stephanie Sapp, Stefan F. Schnabl, Jon Vaver | 2020-03-31 |
| 10282357 | Dynamic resampling for ranking viewer experiences | William Halpin, Antonella Pavese, Harrison Gordon, Kirsten Paige Yee, Yueqing Wang +4 more | 2019-05-07 |
| 8576867 | Pipeline scheduler with fairness and minimum bandwidth guarantee | Chi-Yu Lu | 2013-11-05 |
| 8189597 | Pipeline scheduler with fairness and minimum bandwidth guarantee | Chi-Yu Lu | 2012-05-29 |
| 7796610 | Pipeline scheduler with fairness and minimum bandwidth guarantee | Chi-Yu Lu | 2010-09-14 |
| 7499454 | Pipeline scheduler with fairness and minimum bandwidth guarantee | Chi-Yu Lu | 2009-03-03 |
| 7340175 | Non-uniform optical waveband aggregator and deaggregator and hierarchical hybrid optical cross-connect system | Ting Wang, Rauf Izmailov, Stephen Weinstein | 2008-03-04 |
| 7042883 | Pipeline scheduler with fairness and minimum bandwidth guarantee | Chi-Yu Lu | 2006-05-09 |
| 6618379 | RRGS-round-robin greedy scheduling for input/output terabit switches | Gopalakrishnan Ramamurthy, Aleksandra Smiljanić | 2003-09-09 |
| 6424622 | Optimal buffer management scheme with dynamic queue length thresholds for ATM switches | Alexander Ishii, Brian L. Mark, Gopalakrishnan Ramamurthy, Qiang Ren | 2002-07-23 |
| 6408005 | Dynamic rate control scheduler for ATM networks | Brian L. Mark, Gopalakrishnan Ramamurthy | 2002-06-18 |
| 6389019 | Time-based scheduler architecture and method for ATM networks | Brian L. Mark, Gopalakrishan Ramamurthy, Alexander Ishii | 2002-05-14 |
| 6324165 | Large capacity, multiclass core ATM switch architecture | Brian L. Mark, Gopalakrishnan Ramamurthy | 2001-11-27 |
| 6104698 | Asynchronous transfer mode exchange system and priority control method | Masayuki Shinohara | 2000-08-15 |
| 6046997 | Asynchronous transfer mode switching method and asynchronous transfer mode switch | — | 2000-04-04 |
| 5913074 | Buffer flow control unit for dynamically counting a number of virtual channels per service class in asynchronous transfer network | Chinatsu Ikeda | 1999-06-15 |
| 5825767 | ATM switch with input and output ports | Nobuyuki Mizukoshi | 1998-10-20 |
| 5412648 | Packet switching system for forwarding packets from input buffers using idle/busy status of output buffers | — | 1995-05-02 |
| 5337308 | Low delay ATM switching system using idle cells stamped with reference time | — | 1994-08-09 |