Issued Patents All Time
Showing 51–75 of 128 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11755798 | Logic circuits with reduced transistor counts | Chi-Lin Liu, Wei-Hsiang Ma, Lee-Chung Lu, Fong-Yuan Chang, Sheng-Hsiung Chen +1 more | 2023-09-12 |
| 11748546 | System and method for back side signal routing | Sheng-Hsiung Chen, Kuo-Nan Yang, Jack Liu | 2023-09-05 |
| 11715733 | Integrated circuit device and method | Wei-Ren Chen, Cheng-Yu Lin, Hui-Zhong Zhuang, Yung-Chen Chien, Huang-Yu Chen +1 more | 2023-08-01 |
| 11704472 | Standard cells and variations thereof within a standard cell library | Sheng-Hsiung Chen, Fong-Yuan Chang, Po-Hsiang Huang, Shao-Huan Wang, XinYong WANG +2 more | 2023-07-18 |
| 11677400 | Level shifter circuit and method of operating the same | Yu-Lun Ou, Ji-Yung LIN, Yung-Chen Chien, Ruei-Wun SUN, Wei-Hsiang Ma +2 more | 2023-06-13 |
| 11664380 | Semiconductor device and method of manufacturing the same | Guo-Huei Wu, Chih-Liang Chen, Hui-Zhong Zhuang, Jung-Chan Yang, Lee-Chung Lu +1 more | 2023-05-30 |
| 11632102 | Low-power flip-flop architecture with high-speed transmission gates | Yung-Chen Chien, Xiangdong Chen, Hui-Zhong Zhuang, Tzu-Ying Lin, Lee-Chung Lu | 2023-04-18 |
| 11621703 | Cell of transmission gate free circuit and integrated circuit layout including the same | Ta-Pen Guo, Chi-Lin Liu, Shang-Chih Hsieh, Li-Chun Tien, Lee-Chung Lu | 2023-04-04 |
| 11574110 | Method of forming an integrated circuit | Jung-Chan Yang, Ting-Wei Chiang, Hui-Zhong Zhuang, Lee-Chung Lu, Li-Chun Tien +3 more | 2023-02-07 |
| 11558040 | Low hold multi-bit flip-flop | Seid Hadi Rasouli, Xiangdong Chen, Tzu-Ying Lin, Yung-Chen Chien, Shao-Lun Chien | 2023-01-17 |
| 11545965 | Clock gating circuit and method of operating the same | Seid Hadi Rasouli, Xiangdong Chen, Tzu-Ying Lin, Yung-Chen Chen, Hui-Zhong Zhuang +1 more | 2023-01-03 |
| 11531802 | Layout context-based cell timing characterization | Zhe-Wei Jiang, Sung-Yen Yeh, Li-Chung Hsu | 2022-12-20 |
| 11526649 | Capacitive isolation structure insert for reversed signals | Cheok-Kei Lei, Chi-Lin Liu, Hui-Zhong Zhuang, Zhe-Wei Jiang, Chien-Hsing Li | 2022-12-13 |
| 11526647 | Isolation circuit between power domains | Chi-Yu Lu, Ting-Wei Chiang, Hui-Zhong Zhuang, Pin-Dai Sue, Jiun-Jia Huang +2 more | 2022-12-13 |
| 11509293 | Footprint for multi-bit flip flop | Po-Chun Wang, Hui-Zhong Zhuang, Chih-Liang Chen, Tzu-Ying Lin | 2022-11-22 |
| 11501052 | Conductor scheme selection and track planning for mixed-diagonal-Manhattan routing | Sheng-Hsiung Chen, Huang-Yu Chen, Chung-Hsing Wang | 2022-11-15 |
| 11495619 | Integrated circuit device with improved layout | Fong-Yuan Chang, Chun-Chen Chen, Po-Hsiang Huang, Lee-Chung Lu, Chung-Te Lin +2 more | 2022-11-08 |
| 11494543 | Layout for integrated circuit and the integrated circuit | Cheok-Kei Lei, Yu Li, Chia-Wei Tseng, Zhe-Wei Jiang, Chi-Lin Liu +3 more | 2022-11-08 |
| 11461528 | Integrated circuit, system for and method of forming an integrated circuit | Jung-Chan Yang, Ting-Wei Chiang, Hui-Zhong Zhuang, Lee-Chung Lu, Li-Chun Tien +3 more | 2022-10-04 |
| 11456728 | Data retention circuit and method | Kai-Chi Huang, Yung-Chen Chien, Chi-Lin Liu, Wei-Hsiang Ma, Shang-Chih Hsieh +1 more | 2022-09-27 |
| 11423204 | System and method for back side signal routing | Sheng-Hsiung Chen, Kuo-Nan Yang, Jack Liu | 2022-08-23 |
| 11362660 | Level shifter circuit and method of operating the same | Yu-Lun Ou, Ji-Yung LIN, Yung-Chen Chien, Ruei-Wun SUN, Wei-Hsiang Ma +2 more | 2022-06-14 |
| 11355395 | Integrated circuit in hybrid row height structure | Hui-Zhong Zhuang, Li-Chung Hsu, Sung-Yen Yeh, Yung-Chen Chien, Jung-Chan Yang +1 more | 2022-06-07 |
| 11270052 | System and method of timing characterization for semiconductor circuit | Chia Hao Tu, Hsueh-Chih Chou, Sang Hoo Dhong, Chi-Lin Liu, Cheng-Chung Lin +1 more | 2022-03-08 |
| 11227084 | Multi-bit standard cell | Hui-Zhong Zhuang, Yung-Chen Chien, Ting-Wei Chiang, Chih-Wei Chang, Xiangdong Chen | 2022-01-18 |