Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12147750 | Multiplexer | Chi-Lin Liu, Shang-Chih Hsieh, Jian-Sing Li, Wei-Hsiang Ma, Yi-Hsun Chen | 2024-11-19 |
| 12106033 | Metal cut optimization for standard cells | Zhe-Wei Jiang, Chi-Yu Lu, Yi-Hsin Ko, Chi-Lin Liu, Hui-Zhong Zhuang | 2024-10-01 |
| 12073162 | Capacitive isolation structure insert for reversed signals | Jerry Chang Jui Kao, Chi-Lin Liu, Hui-Zhong Zhuang, Zhe-Wei Jiang, Chien-Hsing Li | 2024-08-27 |
| 11907633 | Layout for integrated circuit and the integrated circuit | Yu Li, Chia-Wei Tseng, Zhe-Wei Jiang, Chi-Lin Liu, Jerry Chang Jui Kao +3 more | 2024-02-20 |
| 11734481 | Metal cut optimization for standard cells | Chi-Lin Liu, Hui-Zhong Zhuang, Zhe-Wei Jiang, Chi-Yu Lu, Yi-Hsin Ko | 2023-08-22 |
| 11694012 | Multiplexer | Chi-Lin Liu, Shang-Chih Hsieh, Jian-Sing Li, Wei-Hsiang Ma, Yi-Hsun Chen | 2023-07-04 |
| 11526649 | Capacitive isolation structure insert for reversed signals | Jerry Chang Jui Kao, Chi-Lin Liu, Hui-Zhong Zhuang, Zhe-Wei Jiang, Chien-Hsing Li | 2022-12-13 |
| 11494543 | Layout for integrated circuit and the integrated circuit | Yu Li, Chia-Wei Tseng, Zhe-Wei Jiang, Chi-Lin Liu, Jerry Chang Jui Kao +3 more | 2022-11-08 |
| 11392743 | Multiplexer | Chi-Lin Liu, Shang-Chih Hsieh, Jian-Sing Li, Wei-Hsiang Ma, Yi-Hsun Chen | 2022-07-19 |
| 11030368 | Metal cut optimization for standard cells | Chi-Lin Liu, Hui-Zhong Zhuang, Zhe-Wei Jiang, Chi-Yu Lu, Yi-Hsin Ko | 2021-06-08 |
| 10943050 | Capacitive isolation structure insert for reversed signals | Jerry Chang Jui Kao, Chi-Lin Liu, Hui-Zhong Zhuang, Zhe-Wei Jiang, Chien-Hsing Li | 2021-03-09 |
| 10691849 | Metal cut optimization for standard cells | Chi-Lin Liu, Hui-Zhong Zhuang, Zhe-Wei Jiang, Chi-Yu Lu, Yi-Hsin Ko | 2020-06-23 |
| 10685162 | Layout for integrated circuit and the integrated circuit | Yu Li, Chia-Wei Tseng, Zhe-Wei Jiang, Chi-Lin Liu, Jerry Chang Jui Kao +3 more | 2020-06-16 |
| 10163883 | Layout method for integrated circuit and layout of the integrated circuit | Yu Li, Chia-Wei Tseng, Zhe-Wei Jiang, Chi-Lin Liu, Jerry Chang Jui Kao +3 more | 2018-12-25 |
| 9659920 | Performance-driven and gradient-aware dummy insertion for gradient-sensitive array | Mu-Jen Huang, Hsiao-Hui Chen, Po-Tsun Chen, Yu Jiang | 2017-05-23 |
| 8978000 | Performance-driven and gradient-aware dummy insertion for gradient-sensitive array | Mu-Jen Huang, Hsiao-Hui Chen, Po-Tsun Chen, Yu Jiang | 2015-03-10 |
| 8875076 | System and methods for converting planar design to FinFET design | Yi-Tang Lin, Shu-Yu Chen, Yu-Ning Chang, Hsiao-Hui Chen, Chih-Sheng Chang +2 more | 2014-10-28 |
| 8789004 | Automatic flow of megacell generation | Hsiao-Hui Chen, Shiue Tsong Shen | 2014-07-22 |
| 8726220 | System and methods for converting planar design to FinFET design | Yi-Tang Lin, Shu-Yu Chen, Yu-Ning Chang, Hsiao-Hui Chen, Chih-Sheng Chang +2 more | 2014-05-13 |
| 8621406 | System and methods for converting planar design to FinFET design | Yi-Tang Lin, Hsiao-Hui Chen, Yu-Ning Chang, Shu-Yu Chen, Chien-Wen Chen +2 more | 2013-12-31 |