Issued Patents All Time
Showing 26–50 of 69 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6215140 | Electrically programmable non-volatile memory cell configuration | Hans Reisinger, Martin Franosch, Herbert Schafer, Volker Lehmann, Gerrit Lange +1 more | 2001-04-10 |
| 6204119 | Manufacturing method for a capacitor in an integrated memory circuit | Gerrit Lange, Martin Franosch, Wolfgang Hönlein, Volker Lehmann, Hans Reisinger +2 more | 2001-03-20 |
| 6197666 | Method for the fabrication of a doped silicon layer | Herbert Schafer, Martin Franosch, Hans Reisinger, Matthias Ilg | 2001-03-06 |
| 6194765 | Integrated electrical circuit having at least one memory cell and method for fabricating it | Hans Reisinger, Ulrike Gruning, Volker Lehmann, Hermann Wendt, Josef Willer +2 more | 2001-02-27 |
| 6165835 | Method for producing a silicon capacitor | Hermann Wendt, Hans Reisinger, Andreas Spitzer, Ulrike Gruning, Josef Willer +2 more | 2000-12-26 |
| 6140177 | Process of forming a semiconductor capacitor including forming a hemispherical grain statistical mask with silicon and germanium | Herbert Schafer, Martin Franosch, Volker Lehmann, Hans Reisinger, Hermann Wendt | 2000-10-31 |
| 6133126 | Method for fabricating a dopant region | Hans Reisinger, Martin Franosch, Herbert Schafer, Volker Lehmann, Gerrit Lange +1 more | 2000-10-17 |
| 6127220 | Manufacturing method for a capacitor in an integrated storage circuit | Gerrit Lange, Martin Franosch, Volker Lehmann, Hans Reisinger, Herbert Schafer +1 more | 2000-10-03 |
| 6117790 | Method for fabricating a capacitor for a semiconductor memory configuration | Herbert Schafer, Martin Franosch, Gerrit Lange, Hans Reisinger, Hermann Wendt +1 more | 2000-09-12 |
| 6054345 | Method for forming deep depletion mode dynamic random access memory (DRAM) cell | Johann Alsmeier | 2000-04-25 |
| 6040995 | Method of operating a storage cell arrangement | Hans Reisinger, Ulrike Gruning, Hermann Wendt, Volker Lehmann, Josef Willer +5 more | 2000-03-21 |
| 6037209 | Method for producing a DRAM cellular arrangement | Wolfgang Rosner, Lothar Risch, Franz Hofmann | 2000-03-14 |
| 6022786 | Method for manufacturing a capacitor for a semiconductor arrangement | Martin Franosch, Wolfgang Hoenlein, Helmut Klose, Gerrit Lange, Volker Lehmann +4 more | 2000-02-08 |
| 6018174 | Bottle-shaped trench capacitor with epi buried layer | Martin Schrems, Jack A. Mandelman, Joachim Hoepfner, Herbert Schaefer | 2000-01-25 |
| 5994746 | Memory cell configuration and method for its fabrication | Hans Reisinger, Franz Hofmann, Wolfgang Krautschneider, Josef Willer | 1999-11-30 |
| 5973385 | Method for suppressing pattern distortion associated with BPSG reflow and integrated circuit chip formed thereby | Jeffrey P. Gambino, Son V. Nguyen | 1999-10-26 |
| 5960318 | Borderless contact etch process with sidewall spacer and selective isotropic etch process | Matthias Peschke, Jeffrey P. Gambino, James G. Ryan | 1999-09-28 |
| 5945704 | Trench capacitor with epi buried layer | Martin Schrems, Jack A. Mandelman, Joachim Hoepfner, Herbert Schaefer | 1999-08-31 |
| 5943571 | Method for manufacturing fine structures | Herbert Schaefer, Martin Franosch, Volker Lehmann, Hans Reisinger, Hermann Wendt | 1999-08-24 |
| 5893735 | Three-dimensional device layout with sub-groundrule features | Erwin Hammerl, Jack A. Mandelman, Herbert L. Ho, Radhika Srinivasan, Alvin P. Short +1 more | 1999-04-13 |
| 5844266 | Buried strap formation in a DRAM trench capacitor | Erwin Hammerl, Herbert L. Ho, Jack A. Mandelman, Radhika Srinivasan, Alvin P. Short | 1998-12-01 |
| 5827765 | Buried-strap formation in a dram trench capacitor | Erwin Hammerl, Herbert L. Ho, Jack A. Mandelman, Radhika Srinivasan, Alvin P. Short | 1998-10-27 |
| 5817553 | Process for manufacturing capacitors in a solid state configuration | Martin Franosch, Hermann Wendt | 1998-10-06 |
| 5804499 | Prevention of abnormal WSi.sub.x oxidation by in-situ amorphous silicon deposition | Christine Dehm, Hans-Joerg Timme | 1998-09-08 |
| 5792685 | Three-dimensional device layout having a trench capacitor | Erwin Hammerl, Jack A. Mandelman, Bernhard Poschenrieder, Alvin P. Short, Radhika Srinivasan +1 more | 1998-08-11 |