Issued Patents All Time
Showing 1–25 of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10881297 | In-situ sensor | Udo Schumacher, Dietmar Schröder | 2021-01-05 |
| 7030434 | Arrangement with image sensors | Heribert Geib, Franz Hofmann, Till Schlosser | 2006-04-18 |
| 6593614 | Integrated circuit configuration having at least one transistor and one capacitor, and method for fabricating it | Franz Hofmann | 2003-07-15 |
| 6576948 | Integrated circuit configuration and method for manufacturing it | Franz Hofmann, Till Schlosser, Josef Willer | 2003-06-10 |
| 6534820 | Integrated dynamic memory cell having a small area of extent, and a method for its production | Franz Hofmann, Till Schlosser | 2003-03-18 |
| 6521935 | Mos transistor and dram cell configuration | Till Schlosser, Josef Willer | 2003-02-18 |
| 6518628 | Integrated CMOS circuit configuration, and production of same | Franz Hofmann, Lothar Risch | 2003-02-11 |
| 6475866 | Method for production of a memory cell arrangement | Franz Hofmann, Josef Willer | 2002-11-05 |
| 6445046 | Memory cell arrangement and process for manufacturing the same | Franz Hofmann, Josef Willer, Hans Reisinger, Paul-Werner von Basse | 2002-09-03 |
| 6442065 | Method for operating a memory cell configuration having dynamic gain memory cells | Franz Hofmann, Till Schlosser, Josef Willer | 2002-08-27 |
| 6438022 | Memory cell configuration | Till Schlosser, Franz Hofmann, Thomas Haneder | 2002-08-20 |
| 6399433 | Method for fabricating a memory cell | Franz Hofmann, Till Schlosser, Josef Willer | 2002-06-04 |
| 6274453 | Memory cell configuration and production process therefor | Till Schlosser, Franz Hofmann | 2001-08-14 |
| 6274431 | Method for manufacturing an integrated circuit arrangement having at least one MOS transistor | Lothar Risch, Wolfgang Roesner, Thomas Aeugle | 2001-08-14 |
| 6265748 | Storage cell arrangement in which vertical MOS transistors have at least three different threshold voltages depending on stored data, and method of producing said arrangement | Franz Hofmann, Josef Willer | 2001-07-24 |
| 6229169 | Memory cell configuration, method for fabricating it and methods for operating it | Franz Hofmann, Wolfgang Rosner, Lothar Risch, Till Schlosser, Paul-Werner Basse | 2001-05-08 |
| 6191459 | Electrically programmable memory cell array, using charge carrier traps and insulation trenches | Franz Hofmann, Josef Willer, Hans Reisinger | 2001-02-20 |
| 6184045 | Method for DRAM cell arrangement and method for its production | Franz Hofman, Lothar Risch, Wolfgang Roesner | 2001-02-06 |
| 6180458 | Method of producing a memory cell configuration | Franz Hofmann, Wolfgang Roesner | 2001-01-30 |
| 6180979 | Memory cell arrangement with vertical MOS transistors and the production process thereof | Franz Hofmann, Josef Willer | 2001-01-30 |
| 6153475 | Method for the manufacturing a memory cell configuration | Franz Hofmann, Josef Willer, Hans Reisinger, Paul-Werner von Basse | 2000-11-28 |
| 6147376 | DRAM cell arrangement and method for its production | Franz Hofman, Lothar Risch, Wolfgang Roesner | 2000-11-14 |
| 6125050 | Configuration for driving parallel lines in a memory cell configuration | Franz Hofmann, Josef Willer, Hans Reisinger, Paul-Werner Basse | 2000-09-26 |
| 6066876 | Integrated circuit arrangement having at least one MOS transistor manufactured by use of a planar transistor layout | Lothar Risch, Wolfgang Roesner, Thomas Aeugle | 2000-05-23 |
| 6064101 | Read-only memory cell arrangement | Frank Lau, Franz Hofmann | 2000-05-16 |