Issued Patents All Time
Showing 101–125 of 210 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11442724 | Pattern recognition | Zhi Peng Jia, Zhi Cao, De Shuo Kong, Jing Wu, Rong Fu He | 2022-09-13 |
| 11423996 | Memory apparatus and method of operation using triple string concurrent programming during erase | Yi Song, Fanqi Wu | 2022-08-23 |
| 11406017 | Flexible printed circuit board, display panel, and display device | Gonghua Zou, Yucheng Lu | 2022-08-02 |
| 11398285 | Memory cell mis-shape mitigation | — | 2022-07-26 |
| 11342028 | Concurrent programming of multiple cells for non-volatile memory devices | Aaron Lee, Gerrit Jan Hemink, Ken Oowada, Toru Miwa | 2022-05-24 |
| 11298459 | Wearable medical device for monitoring intravenous injection | Jing Du, Tzu-Chen Chao, Ci-Wei Lan, Chao Zhang, Xin Hao | 2022-04-12 |
| 11250926 | Positive feedback and parallel searching enhanced optimal read method for non-volatile memory | Jianzhi Wu | 2022-02-15 |
| 11250917 | Dynamic bit line voltage and sensing time enhanced read for data recovery | Jianzhi Wu | 2022-02-15 |
| 11094386 | Device, system, and method to verify data programming of a multi-level cell memory based on one of temperature, pressure, wear condition or relative position of the memory cell | Tarek Ahmed Ameen Beshari, Narayanan Ramanan, Arun Thathachary, Shantanu R. Rajwade, Matin Amani | 2021-08-17 |
| 11081198 | Non-volatile memory with countermeasure for over programming | Gerrit Jan Hemink | 2021-08-03 |
| 11081195 | Programming process which compensates for data state of adjacent memory cell in a memory device | — | 2021-08-03 |
| 11081197 | Wordline voltage overdrive methods and systems | Yu-Chung Lien | 2021-08-03 |
| 11081179 | Pre-charge voltage for inhibiting unselected NAND memory cell programming | — | 2021-08-03 |
| 11081180 | Memory device with bit lines disconnected from NAND strings for fast programming | Huai-Yuan Tseng, Deepanshu Dutta | 2021-08-03 |
| 11056203 | Boosted bitlines for storage cell programmed state verification in a memory array | Pranav Kalavade, Ali Khakifirooz, Shantanu R. Rajwade, Sagar Upadhyay | 2021-07-06 |
| 11017869 | Programming process combining adaptive verify with normal and slow programming speeds in a memory device | Huai-Yuan Tseng, Deepanshu Dutta | 2021-05-25 |
| 11011242 | Bit line voltage control for damping memory programming | Deepanshu Dutta, Gerrit Jan Hemink, Tai-Yuan Tseng, Yan Li | 2021-05-18 |
| 11004524 | SSD having a parallelized, multi-level program voltage verification | Shantanu R. Rajwade, Ali Khakifirooz, Tarek Ahmed Ameen Beshari | 2021-05-11 |
| 10984876 | Temperature based programming in memory | Piyush Dak, Mohan Dunga, Chao Qin, Muhammad Masuduzzaman | 2021-04-20 |
| 10978160 | Mitigating grown bad blocks | Jianzhi Wu, Jun Wan | 2021-04-13 |
| 10978156 | Concurrent programming of multiple cells for non-volatile memory devices | Aaron Lee, Gerrit Jan Hemink, Ken Oowada, Toru Miwa | 2021-04-13 |
| 10930355 | Row dependent sensing in nonvolatile memory | Huai-Yuan Tseng, Deepanshu Dutta | 2021-02-23 |
| 10910083 | Leaky memory hole repair at fabrication joint | Gerrit Jan Hemink | 2021-02-02 |
| 10910060 | Select line voltage waveform real-time monitor for non-volatile memory | Jianzhi Wu | 2021-02-02 |
| 10910075 | Programming process combining adaptive verify with normal and slow programming speeds in a memory device | Huai-Yuan Tseng, Deepanshu Dutta | 2021-02-02 |