Issued Patents All Time
Showing 126–150 of 210 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10910076 | Memory cell mis-shape mitigation | — | 2021-02-02 |
| 10885994 | Interleaved program and verify in non-volatile memory | Huai-Yuan Tseng, Deepanshu Dutta | 2021-01-05 |
| 10878923 | Partial page sensing mode, method, and apparatus for 3D NAND | Yu-Chung Lien | 2020-12-29 |
| 10861571 | Wordline voltage overdrive methods and systems | Yu-Chung Lien | 2020-12-08 |
| 10839928 | Non-volatile memory with countermeasure for over programming | Gerrit Jan Hemink | 2020-11-17 |
| 10839915 | Bitline boost for nonvolatile memory | Ohwon Kwon | 2020-11-17 |
| 10839922 | Memory disturb detection | Huai-Yuan Tseng, Deepanshu Dutta | 2020-11-17 |
| 10839923 | Predictive boosting for 3D NAND | — | 2020-11-17 |
| 10832778 | Negative voltage wordline methods and systems | Huai-Yuan Tseng, Deepanshu Dutta | 2020-11-10 |
| 10811089 | Adaptive programming voltage for non-volatile memory devices | Huai-Yuan Tseng, Deepanshu Dutta | 2020-10-20 |
| 10741257 | Dynamic bit line voltage and sensing time enhanced read for data recovery | Jianzhi Wu | 2020-08-11 |
| 10734070 | Programming selection devices in non-volatile memory strings | Dengtao Zhao, Huai-Yuan Tseng, Deepanshu Dutta, Zhongguang Xu, Yanli Zhang +1 more | 2020-08-04 |
| 10726923 | Bias scheme for dummy lines of data storage devices | — | 2020-07-28 |
| 10726920 | Pre-charge voltage for inhibiting unselected NAND memory cell programming | — | 2020-07-28 |
| 10726929 | Programming process which compensates for data state of adjacent memory cell in a memory device | — | 2020-07-28 |
| 10726922 | Memory device with connected word lines for fast programming | Huai-Yuan Tseng, Deepanshu Dutta | 2020-07-28 |
| 10714198 | Dynamic 1-tier scan for high performance 3D NAND | Deepanshu Dutta, Huai-Yuan Tseng | 2020-07-14 |
| 10707226 | Source side program, method, and apparatus for 3D NAND | Brian Murphy, Lito De La Rama | 2020-07-07 |
| 10643684 | Double sense program verification of a memory array | — | 2020-05-05 |
| 10643692 | Adaptive programming voltage for non-volatile memory devices | Huai-Yuan Tseng, Deepanshu Dutta | 2020-05-05 |
| 10643720 | Bit line voltage control for damping memory programming | Deepanshu Dutta, Gerrit Jan Hemink, Tai-Yuan Tseng, Yan Li | 2020-05-05 |
| 10643721 | Interleaved program and verify in non-volatile memory | Huai-Yuan Tseng, Deepanshu Dutta | 2020-05-05 |
| 10636487 | Memory device with bit lines disconnected from NAND strings for fast programming | Huai-Yuan Tseng, Deepanshu Dutta | 2020-04-28 |
| 10636498 | Managing bit-line settling time in non-volatile memory | Yu-Chung Lien, Zhenming Zhou, Deepanshu Dutta | 2020-04-28 |
| 10636503 | Alteration of sensing time in memory cells | — | 2020-04-28 |