Issued Patents All Time
Showing 51–75 of 210 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11972808 | Recovery pulses to counter cumulative read disturb | Abhijith Prakash | 2024-04-30 |
| 11972806 | Read techniques to reduce read errors in a memory device | Jiacen Guo | 2024-04-30 |
| 11972108 | Parameter redundancy reduction method | Zhong Fang Yuan, Tong Liu, Li Gao, Na Liu | 2024-04-30 |
| 11961572 | Edge word line data retention improvement for memory apparatus with on-pitch semi-circle drain side select gate technology | Abhijith Prakash, Shubhajit Mukherjee | 2024-04-16 |
| 11961573 | Memory device that is optimized for operation at different temperatures | Abhijith Prakash, Dengtao Zhao | 2024-04-16 |
| 11955184 | Memory cell group read with compensation for different programming speeds | Jiacen Guo, Xiaochen Zhu, Lito De La Rama, Yi Song, Jiahui Yuan | 2024-04-09 |
| 11942157 | Variable bit line bias for nonvolatile memory | Jiacen Guo, Xiaochen Zhu | 2024-03-26 |
| 11935593 | Dummy cell resistance tuning in NAND strings | Yi Song, Jiahui Yuan | 2024-03-19 |
| 11935585 | Pseudo multi-plane read methods and apparatus for non-volatile memory devices | Arka Ganguly, Ohwon Kwon | 2024-03-19 |
| 11894064 | Sub-block mode for non-volatile memory | — | 2024-02-06 |
| 11894073 | Proactive refresh of edge data word line for semi-circle drain side select gate | — | 2024-02-06 |
| 11894072 | Two-side staircase pre-charge in sub-block mode of three-tier non-volatile memory architecture | Jiacen Guo, Abhijith Prakash | 2024-02-06 |
| 11894067 | Method to fix cumulative read induced drain side select gate downshift in memory apparatus with on-pitch drain side select gate | Abhijith Prakash, Shubhajit Mukherjee | 2024-02-06 |
| 11894062 | Semi-circle drain side select gate maintenance by selective semi-circle dummy word line program | Deepanshu Dutta, Gerrit Jan Hemink, Shubhajit Mukherjee | 2024-02-06 |
| 11881271 | Non-volatile memory with engineered channel gradient | Jiacen Guo, Xiaochen Zhu | 2024-01-23 |
| 11881266 | Neighbor bit line coupling enhanced gate-induced drain leakage erase for memory apparatus with on-pitch semi-circle drain side select gate technology | Kou Tei, Ohwon Kwon | 2024-01-23 |
| 11871580 | Three-dimensional memory device including low-k drain-select-level isolation structures and methods of forming the same | Peng Zhang, Yanli Zhang, Koichi Matsuno, Masaaki Higashitani, Johann Alsmeier | 2024-01-09 |
| 11862249 | Non-volatile memory with staggered ramp down at the end of pre-charging | Fanqi Wu, Jiacen Guo, Jiahui Yuan | 2024-01-02 |
| 11848059 | Techniques for erasing the memory cells of edge word lines | Jiacen Guo, Abhijith Prakash | 2023-12-19 |
| 11848847 | Balanced optimization within a broker cluster | Jun Guo, Yong Wang, Deng Xin Luo, Jia He | 2023-12-19 |
| 11837292 | String or block or die level dependent source line voltage for neighbor drain side select gate interference compensation | Jiacen Guo | 2023-12-05 |
| 11837297 | Smart erase verify in non-volatile memory structures | — | 2023-12-05 |
| 11823744 | Programming techniques for memory devices having partial drain-side select gates | — | 2023-11-21 |
| 11803709 | Computer-assisted topic guidance in document writing | Wen Jie Hao, Zhong Fang Yuan, Wang Hu Dang, Deng Xin Luo, Jia Yong Xie +1 more | 2023-10-31 |
| 11798625 | Program dependent biasing of unselected sub-blocks | Deepanshu Dutta, Gerrit Jan Hemink | 2023-10-24 |