Issued Patents All Time
Showing 51–75 of 156 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9748479 | Memory cells including vertically oriented adjustable resistance structures | Juan Saenz | 2017-08-29 |
| 9735202 | Implementation of VMCO area switching cell to VBL architecture | Yoichiro Tanaka, Yangyin Chen, Chu-Chen Fu | 2017-08-15 |
| 9734009 | Data encoding techniques for a device | Xinde Hu, Eran Sharon, Idan Alrod, Ariel Navon | 2017-08-15 |
| 9711222 | Content addressable memory cells and memory arrays | — | 2017-07-18 |
| RE46435 | Three dimensional hexagonal matrix memory array | Roy E. Scheuerlein | 2017-06-13 |
| 9627009 | Interleaved grouped word lines for three dimensional non-volatile storage | — | 2017-04-18 |
| 9583615 | Vertical transistor and local interconnect structure | Yung-Tin Chen, Guangle Zhou | 2017-02-28 |
| 9576657 | Memory cells including vertically oriented adjustable resistance structures | Juan Saenz | 2017-02-21 |
| 9502471 | Multi tier three-dimensional memory devices including vertically shared bit lines | Zhenyu Lu, Henry Chien, Johann Alsmeier, Koji Miyata, Tong Zhang +7 more | 2016-11-22 |
| 9484093 | Controlling adjustable resistance bit lines connected to word line combs | Perumal Ratnam, Tianhong Yan | 2016-11-01 |
| 9478495 | Three dimensional memory device containing aluminum source contact via structure and method of making thereof | Jayavel Pachamuthu, Peter Rabkin, Jilin Xia | 2016-10-25 |
| 9472758 | High endurance non-volatile storage | Zhida Lan, Abhijit Bandyopadhyay, Li Xiao, Girish Nagavarapu | 2016-10-18 |
| 9472301 | Dielectric-based memory cells having multi-level one-time programmable and bi-level rewriteable operating modes and methods of forming the same | Abhijit Bandyopadhyay, Tanmay Kumar, Scott Brad Herner, Roy E. Scheuerlein | 2016-10-18 |
| 9455301 | Setting channel voltages of adjustable resistance bit line structures using dummy word lines | Perumal Ratnam, Tianhong Yan | 2016-09-27 |
| 9443910 | Silicided bit line for reversible-resistivity memory | Kan Fujiwara, Takuya Futase, Toshihiro Iizuka, Shin Kikuchi, Yoichiro Tanaka +1 more | 2016-09-13 |
| 9443590 | Content addressable memory cells, memory arrays and methods of forming the same | — | 2016-09-13 |
| 9373396 | Side wall bit line structures | Perumal Ratnam, Tianhong Yan | 2016-06-21 |
| 9369553 | Mobile electronic device comprising an ultrathin sapphire cover plate | James M. Zahler | 2016-06-14 |
| 9099385 | Vertical 1T-1R memory cells, memory arrays and methods of forming the same | — | 2015-08-04 |
| 9082786 | Method of fabricating a self-aligning damascene memory structure | Kang-Jay Hsia, Calvin K. Li | 2015-07-14 |
| 8969923 | Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning | Roy E. Scheuerlein, Yoichiro Tanaka | 2015-03-03 |
| 8921686 | Back-contact photovoltaic cell comprising a thin lamina having a superstrate receiver element | Steven M. Zuniga, Gopal Prabhu | 2014-12-30 |
| 8884357 | Vertical NAND and method of making thereof using sequential stack etching and landing pad | Chi-Ming Wang, Johann Alsmeier, Henry Chien, Xiying Costa, Yung-Tin Chen | 2014-11-11 |
| 8871608 | Method for fabricating backside-illuminated sensors | Venkatesan Murali, Arvind Chari, Gopal Prabhu | 2014-10-28 |
| 8822260 | Asymmetric surface texturing for use in a photovoltaic cell and method of making | — | 2014-09-02 |