Issued Patents All Time
Showing 101–125 of 156 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7982273 | Masking of repeated overlay and alignment marks to allow reuse of photomasks in a vertical structure | Yung-Tin Chen, Steven J. Radigan, Tanmay Kumar | 2011-07-19 |
| 7964431 | Method to make electrical contact to a bonded face of a photovoltaic cell | Mohamed M. Hilali | 2011-06-21 |
| 7928007 | Method for reducing dielectric overetch when making contact to conductive features | — | 2011-04-19 |
| 7927990 | Forming complimentary metal features using conformal insulator layer | Kang-Jay Hsia, Calvin K. Li | 2011-04-19 |
| 7915522 | Asymmetric surface texturing for use in a photovoltaic cell and method of making | — | 2011-03-29 |
| 7888200 | Embedded memory in a CMOS circuit and methods of forming the same | — | 2011-02-15 |
| 7887999 | Method of making a pillar pattern using triple or quadruple exposure | Roy E. Scheuerlein | 2011-02-15 |
| 7868388 | Embedded memory in a CMOS circuit and methods of forming the same | — | 2011-01-11 |
| 7858430 | Method for making a photovoltaic cell comprising contact regions doped through a lamina | Mohamed M. Hilali, S. Brad Herner | 2010-12-28 |
| 7855119 | Method for forming polycrystalline thin film bipolar transistors | S. Brad Herner | 2010-12-21 |
| 7842585 | Method to form a photovoltaic cell comprising a thin lamina | Srinivasan Sivaram, Aditya Agarwal, S. Brad Herner | 2010-11-30 |
| 7812404 | Nonvolatile memory cell comprising a diode and a resistance-switching material | S. Brad Herner, Tanmay Kumar | 2010-10-12 |
| 7800933 | Method for using a memory cell comprising switchable semiconductor memory element with trimmable resistance | Tanmay Kumar, S. Brad Herner, Roy E. Scheuerlein | 2010-09-21 |
| 7800939 | Method of making 3D R/W cell with reduced reverse leakage | Tanmay Kumar | 2010-09-21 |
| 7800934 | Programming methods to increase window for reverse write 3D cell | Tanmay Kumar, S. Brad Herner | 2010-09-21 |
| 7790534 | Method to form low-defect polycrystalline semiconductor material for use in a transistor | S. Brad Herner | 2010-09-07 |
| 7790607 | Method for reducing dielectric overetch using a dielectric etch stop at a planar surface | Samuel V. Dunton, Usha Raghuram | 2010-09-07 |
| 7786015 | Method for fabricating self-aligned complementary pillar structures and wiring | Yung-Tin Chen, Chun-Ming Wang, Steven J. Radigan, Steven Maxwell | 2010-08-31 |
| 7759201 | Method for fabricating pitch-doubling pillar structures | Steven J. Radigan | 2010-07-20 |
| 7759666 | 3D R/W cell with reduced reverse leakage | Tanmay Kumar | 2010-07-20 |
| 7745312 | Selective germanium deposition for pillar devices | S. Brad Herner | 2010-06-29 |
| 7746680 | Three dimensional hexagonal matrix memory array | Roy E. Scheuerlein | 2010-06-29 |
| 7706177 | Method of programming cross-point diode memory array | — | 2010-04-27 |
| 7629247 | Method of fabricating a self-aligning damascene memory structure | Kang-Jay Hsia, Calvin K. Li | 2009-12-08 |
| 7570523 | Method for using two data busses for memory array block selection | Roy E. Scheuerlein, Luca Fasoli | 2009-08-04 |