Issued Patents All Time
Showing 151–156 of 156 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6784552 | Structure having reduced lateral spacer erosion | James E. Nulty | 2004-08-31 |
| 6501139 | High-voltage transistor and fabrication process | — | 2002-12-31 |
| 6359316 | Method and apparatus to prevent latch-up in CMOS devices | Peter Voss, Andrew J. Walker, Jeff Watt, Ashish Pancholy, Cathal G. Phelan +1 more | 2002-03-19 |
| 6066555 | Method for eliminating lateral spacer erosion on enclosed contact topographies during RF sputter cleaning | James E. Nulty | 2000-05-23 |
| 5654915 | 6-bulk transistor static memory cell using split wordline architecture | Andre Stolmeijer | 1997-08-05 |
| 5523258 | Method for avoiding lithographic rounding effects for semiconductor fabrication | Andre Stolmeijer, Mark A. Helm | 1996-06-04 |