Issued Patents All Time
Showing 1–25 of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11016600 | Latency reduction in touch sensitive systems | Owen Drumm | 2021-05-25 |
| 8825925 | Systems and methods for super speed packet transfer | Gaurav Singh, Herve Jacques Clement Letourneur, Hans Van Antwerpen | 2014-09-02 |
| 6839778 | Speed power efficient USB method | Ronald H. Sartore, Steven P. Larky | 2005-01-04 |
| 6651134 | Memory device with fixed length non interruptible burst | — | 2003-11-18 |
| 6556487 | Non-volatile static memory cell | Nirmal Ratnakumar, Kenelm G. D. Murray | 2003-04-29 |
| 6499089 | Method, architecture and circuitry for independently configuring a multiple array memory device | Scott Harmel, Rajesh Manapat, Sunil Koduru | 2002-12-24 |
| 6445645 | Random access memory having independent read port and write port and process for writing to and reading from the same | Mathew R. Arcoleo, Ashish Pancholy, Simon J. Lovett | 2002-09-03 |
| 6388927 | Direct bit line-bit line defect detection test mode for SRAM | Jonathan F. Churchill, Jeffrey F. Kooiman, Ashish Pancholy, Gary A. Gibbs | 2002-05-14 |
| 6385128 | Random access memory having a read/write address bus and process for writing to and reading from the same | Mathew R. Arcoleo, Ashish Pancholy, Simon J. Lovett | 2002-05-07 |
| 6363031 | Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit | — | 2002-03-26 |
| 6359316 | Method and apparatus to prevent latch-up in CMOS devices | Peter Voss, Andrew J. Walker, Jeff Watt, Ashish Pancholy, Patrick Zicolello +1 more | 2002-03-19 |
| 6292403 | Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method | Ashish Pancholy, Simon J. Lovett | 2001-09-18 |
| 6286118 | Scan path circuitry including a programmable delay circuit | Jonathan F. Churchill, Neil P. Raftery, Colin J. Hendry, Jeyakumar Shanmugam, Mark A. Finn +2 more | 2001-09-04 |
| 6262937 | Synchronous random access memory having a read/write address bus and process for writing to and reading from the same | Mathew R. Arcoleo, Ashish Pancholy, Simon J. Lovett | 2001-07-17 |
| 6262936 | Random access memory having independent read port and write port and process for writing to and reading from the same | Mathew R. Arcoleo, Ashish Pancholy, Simon J. Lovett | 2001-07-17 |
| 6256249 | Method for hidden DRAM refresh | — | 2001-07-03 |
| 6166991 | Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit | — | 2000-12-26 |
| 6115836 | Scan path circuitry for programming a variable clock pulse width | Jonathan F. Churchill, Neil P. Raftery, Colin J. Hendry, Jeyakumar Shanmugam, Mark A. Finn +2 more | 2000-09-05 |
| 6069839 | Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method | Ashish Pancholy, Simon J. Lovett | 2000-05-30 |
| 6006347 | Test mode features for synchronous pipelined memories | Jonathan F. Churchill, Neil P. Raftery, Colin J. Hendry, Jeyakumar Shanmugam, Mark A. Finn +2 more | 1999-12-21 |
| 5953285 | Scan path circuitry including an output register having a flow through mode | Jonathan F. Churchill, Neil P. Raftery, Jeyakumar Shanmugam, Mark A. Finn, Thomas M. Surrette +1 more | 1999-09-14 |
| 5936977 | Scan path circuitry including a programmable delay circuit | Jonathan F. Churchill, Neil P. Raftery, Colin J. Hendry, Jeyakumar Shanmugam, Mark A. Finn +2 more | 1999-08-10 |
| 5677555 | Output driver transistor with multiple gate bodies | Kent M. Kalpakjian | 1997-10-14 |
| 5525919 | Sense amplifier with limited output voltage swing | — | 1996-06-11 |
| 5504443 | Differential latch sense amlifiers using feedback | Eric Gross | 1996-04-02 |