Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7126391 | Power on reset circuits | Sean M. Smith, James Lutley | 2006-10-24 |
| 6981238 | Verification of integrated circuit designs using buffer control | — | 2005-12-27 |
| 6724232 | Dual tristate path output buffer control | — | 2004-04-20 |
| 6538485 | Dual tristate path output buffer control | — | 2003-03-25 |
| 6404682 | Wired address compare circuit and method | James Lutley, Neil P. Raftery, Kenneth A. Maher | 2002-06-11 |
| 6392941 | Wordline and pseudo read stress test for SRAM | — | 2002-05-21 |
| 6388927 | Direct bit line-bit line defect detection test mode for SRAM | Jeffrey F. Kooiman, Cathal G. Phelan, Ashish Pancholy, Gary A. Gibbs | 2002-05-14 |
| 6288948 | Wired address compare circuit and method | James Lutley, Neil P. Raftery, Kenneth A. Maher | 2001-09-11 |
| 6286118 | Scan path circuitry including a programmable delay circuit | Neil P. Raftery, Colin J. Hendry, Jeyakumar Shanmugam, Mark A. Finn, Thomas M. Surrette +2 more | 2001-09-04 |
| 6115836 | Scan path circuitry for programming a variable clock pulse width | Neil P. Raftery, Colin J. Hendry, Jeyakumar Shanmugam, Mark A. Finn, Thomas M. Surrette +2 more | 2000-09-05 |
| 6006347 | Test mode features for synchronous pipelined memories | Neil P. Raftery, Colin J. Hendry, Jeyakumar Shanmugam, Mark A. Finn, Thomas M. Surrette +2 more | 1999-12-21 |
| 5953285 | Scan path circuitry including an output register having a flow through mode | Neil P. Raftery, Jeyakumar Shanmugam, Mark A. Finn, Thomas M. Surrette, Cathal G. Phelan +1 more | 1999-09-14 |
| 5936977 | Scan path circuitry including a programmable delay circuit | Neil P. Raftery, Colin J. Hendry, Jeyakumar Shanmugam, Mark A. Finn, Thomas M. Surrette +2 more | 1999-08-10 |
| 5907255 | Dynamic voltage reference which compensates for process variations | — | 1999-05-25 |
| 5852579 | Method and circuit for preventing and/or inhibiting contention in a system employing a random access memory | Mathew R. Arcoleo, Raymond M. Leong, Derek Johnson | 1998-12-22 |
| 5570043 | Overvoltage tolerant intergrated circuit output buffer | — | 1996-10-29 |