Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11600180 | Method and apparatus for optimizing efficiency of a transport provider | Yuki KAMIYA, Konstantinos Gkiotsalitis, Nitin Maslekar | 2023-03-07 |
| 6526495 | Multiport FIFO with programmable width and depth | Piyush Sevalia | 2003-02-25 |
| 6131140 | Integrated cache memory with system control logic and adaptation of RAM bus to a cache pinout | Thurman J. Rodgers, Peter Voss, Tek Wei | 2000-10-10 |
| 5963499 | Cascadable multi-channel network memory with dynamic allocation | Derek Johnson, Mathew R. Arcoleo | 1999-10-05 |
| 5864506 | Memory having selectable output strength | Mathew R. Arcoleo, Derek Johnson | 1999-01-26 |
| 5860085 | Instruction set for a content addressable memory array with read/write circuits and an interface register logic block | Charles D. Stormon, Edward Saleh, Nikos B. Troullinos | 1999-01-12 |
| 5852579 | Method and circuit for preventing and/or inhibiting contention in a system employing a random access memory | Mathew R. Arcoleo, Derek Johnson, Jonathan F. Churchill | 1998-12-22 |
| 5732027 | Memory having selectable output strength | Mathew R. Arcoleo, Derek Johnson | 1998-03-24 |
| 5649149 | Integrated content addressable memory array with processing logical and a host computer interface | Charles D. Stormon, Abhijeet V. Chavan, Nikos B. Troullinos | 1997-07-15 |
| 5212663 | Method to implement a large resettable static RAM without the large surge current | — | 1993-05-18 |