Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6286118 | Scan path circuitry including a programmable delay circuit | Jonathan F. Churchill, Neil P. Raftery, Colin J. Hendry, Jeyakumar Shanmugam, Mark A. Finn +2 more | 2001-09-04 |
| 6115836 | Scan path circuitry for programming a variable clock pulse width | Jonathan F. Churchill, Neil P. Raftery, Colin J. Hendry, Jeyakumar Shanmugam, Mark A. Finn +2 more | 2000-09-05 |
| 6006347 | Test mode features for synchronous pipelined memories | Jonathan F. Churchill, Neil P. Raftery, Colin J. Hendry, Jeyakumar Shanmugam, Mark A. Finn +2 more | 1999-12-21 |
| 5953285 | Scan path circuitry including an output register having a flow through mode | Jonathan F. Churchill, Neil P. Raftery, Jeyakumar Shanmugam, Mark A. Finn, Cathal G. Phelan +1 more | 1999-09-14 |
| 5936977 | Scan path circuitry including a programmable delay circuit | Jonathan F. Churchill, Neil P. Raftery, Colin J. Hendry, Jeyakumar Shanmugam, Mark A. Finn +2 more | 1999-08-10 |