Issued Patents All Time
Showing 126–150 of 156 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7554832 | Passive element memory array incorporating reversible polarity word line and bit line decoders | Luca Fasoli, Roy E. Scheuerlein | 2009-06-30 |
| 7553611 | Masking of repeated overlay and alignment marks to allow reuse of photomasks in a vertical structure | Yung-Tin Chen, Steven J. Radigan, Tanmay Kumar | 2009-06-30 |
| 7525137 | TFT mask ROM and method for making same | Andrew J. Walker | 2009-04-28 |
| 7521353 | Method for reducing dielectric overetch when making contact to conductive features | — | 2009-04-21 |
| 7505321 | Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same | Roy E. Scheuerlein, Andrew J. Walker, En-Hsing Chen, Sucheta Nallamothu, Alper Ilkbahar +2 more | 2009-03-17 |
| 7499355 | High bandwidth one time field-programmable memory | Roy E. Scheuerlein | 2009-03-03 |
| 7499304 | Systems for high bandwidth one time field-programmable memory | Roy E. Scheuerlein | 2009-03-03 |
| 7486537 | Method for using a mixed-use memory array with different data states | Roy E. Scheuerlein | 2009-02-03 |
| 7474000 | High density contact to relaxed geometry layers | Roy E. Scheuerlein | 2009-01-06 |
| 7463536 | Memory array incorporating two data busses for memory array block selection | Roy E. Scheuerlein, Luca Fasoli | 2008-12-09 |
| 7463546 | Method for using a passive element memory array incorporating reversible polarity word line and bit line decoders | Luca Fasoli, Roy E. Scheuerlein | 2008-12-09 |
| 7422985 | Method for reducing dielectric overetch using a dielectric etch stop at a planar surface | Samuel V. Dunton, Usha Raghuram | 2008-09-09 |
| 7272052 | Decoding circuit for non-binary groups of memory line drivers | Roy E. Scheuerlein, Luca Fasoli | 2007-09-18 |
| 7250646 | TFT mask ROM and method for making same | Andrew J. Walker | 2007-07-31 |
| 7177227 | Transistor layout configuration for tight-pitched memory array lines | Roy E. Scheuerlein, Tanmay Kumar, Abhijit Bandyopadhyay | 2007-02-13 |
| 7129538 | Dense arrays and charge storage devices | Thomas H. Lee, Vivek Subramanian, James M. Cleeves, Andrew J. Walker, Igor G. Kouznetzov +3 more | 2006-10-31 |
| 7101764 | High-voltage transistor and fabrication process | — | 2006-09-05 |
| 7054219 | Transistor layout configuration for tight-pitched memory array lines | Roy E. Scheuerlein, Tanmay Kumar, Abhijit Bandyopadhyay | 2006-05-30 |
| 7005350 | Method for fabricating programmable memory array structures incorporating series-connected transistor strings | Andrew J. Walker, En-Hsing Chen, Sucheta Nallamothu, Roy E. Scheuerlein, Alper Ilkbahar +2 more | 2006-02-28 |
| 6992349 | Rail stack array of charge storage devices and method of making same | Thomas H. Lee, Andrew J. Walker, Igor G. Kouznetzov | 2006-01-31 |
| 6946719 | Semiconductor device including junction diode contacting contact-antifuse unit comprising silicide | S. Brad Herner | 2005-09-20 |
| 6888750 | Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication | Andrew J. Walker, Mark G. Johnson, N. Johan Knall, Igor G. Kouznetsov | 2005-05-03 |
| 6881994 | Monolithic three dimensional array of charge storage devices containing a planarized surface | Thomas H. Lee, Vivek Subramanian, James M. Cleeves, Andrew J. Walker, Igor G. Kouznetzov +3 more | 2005-04-19 |
| 6841813 | TFT mask ROM and method for making same | Andrew J. Walker | 2005-01-11 |
| 6815781 | Inverted staggered thin film transistor with salicided source/drain structures and method of making same | Michael A. Vyvoda, S. Brad Herner, Andrew J. Walker | 2004-11-09 |