Issued Patents All Time
Showing 76–100 of 156 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8809128 | Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning | Roy E. Scheuerlein, Yoichiro Tanaka | 2014-08-19 |
| 8785294 | Silicon carbide lamina | Venkatesan Murali, Steve Babayan | 2014-07-22 |
| 8748859 | Non-volatile memory arrays comprising rail stacks with a shared diode component portion for diodes of electrically isolated pillars | Kang-Jay Hsia, Calvin K. Li | 2014-06-10 |
| 8741768 | Method for reducing dielectric overetch when making contact to conductive features | — | 2014-06-03 |
| 8741696 | Methods of forming pillars for memory cells using sequential sidewall patterning | Roy E. Scheuerlein, Yoichiro Tanaka | 2014-06-03 |
| 8687410 | Nonvolatile memory cell comprising a diode and a resistance-switching material | Scott Brad Herner, Tanmay Kumar | 2014-04-01 |
| 8633105 | Method of fabricating a self-aligning damascene memory structure | Kang-Jay Hsia, Calvin K. Li | 2014-01-21 |
| 8633374 | Photovoltaic cell comprising contact regions doped through a lamina | Mohamed M. Hilali, S. Brad Herner | 2014-01-21 |
| 8536448 | Zener diode within a diode structure providing shunt protection | — | 2013-09-17 |
| 8518724 | Method to form a device by constructing a support element on a thin semiconductor lamina | Mohamed M. Hilali, Theodore H. Smick, Venkatesan Murali, Kathy J. Jackson, Zhiyong Li +1 more | 2013-08-27 |
| 8501522 | Intermetal stack for use in a photovoltaic cell | S. Brad Herner, Mark Clark | 2013-08-06 |
| 8497204 | Method for reducing dielectric overetch when making contact to conductive features | — | 2013-07-30 |
| 8481845 | Method to form a photovoltaic cell comprising a thin lamina | Srinivasan Sivaram, Aditya Agarwal, S. Brad Herner | 2013-07-09 |
| 8410353 | Asymmetric surface texturing for use in a photovoltaic cell and method of making | — | 2013-04-02 |
| 8389399 | Method of fabricating a self-aligning damascene memory structure | Kang-Jay Hsia, Calvin K. Li | 2013-03-05 |
| 8349664 | Nonvolatile memory cell comprising a diode and a resistance-switching material | Scott Brad Herner, Tanmay Kumar | 2013-01-08 |
| 8338209 | Photovoltaic cell comprising a thin lamina having a rear junction and method of making | Mohamed M. Hilali | 2012-12-25 |
| 8247260 | Method to form a photovoltaic cell comprising a thin lamina | Srinivasan Sivaram, Aditya Agarwal, S. Brad Herner | 2012-08-21 |
| 8173452 | Method to form a device by constructing a support element on a thin semiconductor lamina | Mohamed M. Hilali, Theodore H. Smick, Venkatesan Murali, Kathy J. Jackson, Zhiyong Li +1 more | 2012-05-08 |
| 8154005 | Non-volatile memory arrays comprising rail stacks with a shared diode component portion for diodes of electrically isolated pillars | Kang-Jay Hsia, Calvin K. Li | 2012-04-10 |
| 8129613 | Photovoltaic cell comprising a thin lamina having low base resistivity and method of making | Mohamed M. Hilali | 2012-03-06 |
| 8107270 | Three dimensional hexagonal matrix memory array | Roy E. Scheuerlein | 2012-01-31 |
| 8101451 | Method to form a device including an annealed lamina and having amorphous silicon on opposing faces | Venkatesan Murali, Theodore H. Smick, Mohamed M. Hilali, Kathy J. Jackson, Zhiyong Li +1 more | 2012-01-24 |
| 8008187 | Method for reducing dielectric overetch using a dielectric etch stop at a planar surface | Samuel V. Dunton, Usha Raghuram | 2011-08-30 |
| 8004013 | Polycrystalline thin film bipolar transistors | S. Brad Herner | 2011-08-23 |