Issued Patents All Time
Showing 26–50 of 156 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10453531 | Content addressable memory using threshold-adjustable vertical transistors and methods of forming the same | — | 2019-10-22 |
| 10388870 | Barrier modulated cell structures with intrinsic vertical bit line architecture | Perumal Ratnam, Tanmay Kumar | 2019-08-20 |
| 10388646 | Electrostatic discharge protection devices including a field-induced switching element | Derek Stewart, Daniel Bedau, Michael Grobis | 2019-08-20 |
| 10381409 | Three-dimensional phase change memory array including discrete middle electrodes and methods of making the same | Fei Zhou, Raghuveer S. Makala, Rahul Sharangpani, Adarsh Rajashekhar, Seung-Yeul Yang | 2019-08-13 |
| 10381559 | Three-dimensional phase change memory array including discrete middle electrodes and methods of making the same | Fei Zhou, Raghuveer S. Makala, Rahul Sharangpani, Adarsh Rajashekhar, Seung-Yeul Yang | 2019-08-13 |
| 10374013 | Methods and apparatus for three-dimensional nonvolatile memory | Abhijit Bandyopadhyay, Natalie Nguyen, Brian Le | 2019-08-06 |
| 10374014 | Multi-state phase change memory device with vertical cross-point structure | Federico Nardi, Gerrit Jan Hemink | 2019-08-06 |
| 10354710 | Magnetoelectric random access memory array and methods of operating the same | Neil Leslie Robertson, Abhijit Bandyopadhyay | 2019-07-16 |
| 10319437 | Apparatus and method for identifying memory cells for data refresh based on monitor cell in a resistive memory device | Juan Saenz | 2019-06-11 |
| 10283562 | Process for fabricating three dimensional non-volatile memory system | Luiz M. Franca-Neto, Mac D. Apodaca | 2019-05-07 |
| 10262730 | Multi-state and confined phase change memory with vertical cross-point structure | Federico Nardi, Gerrit Jan Hemink | 2019-04-16 |
| 10249682 | Non-volatile memory system with serially connected non-volatile reversible resistance-switching memory cells | Luiz M. Franca-Neto, Mac D. Apodaca | 2019-04-02 |
| 10217795 | Memory cell for non-volatile memory system | Luiz M. Franca-Neto, Mac D. Apodaca | 2019-02-26 |
| 10109679 | Wordline sidewall recess for integrating planar selector device | Yangyin Chen | 2018-10-23 |
| 10056399 | Three-dimensional memory devices containing inter-tier dummy memory cells and methods of making the same | Xiying Costa, Daxin Mao, Dana Lee, Yao-Sheng Lee | 2018-08-21 |
| 10038092 | Three-level ferroelectric memory cell using band alignment engineering | Yangyin Chen | 2018-07-31 |
| 10032908 | Multi-gate vertical field effect transistor with channel strips laterally confined by gate dielectric layers, and method of making thereof | Perumal Ratnam, Juan Saenz, Guangle Zhou, Abhijit Bandyopadhyay, Tanmay Kumar | 2018-07-24 |
| 10026782 | Implementation of VMCO area switching cell to VBL architecture | Yoichiro Tanaka, Yangyin Chen, Chu-Chen Fu | 2018-07-17 |
| 9941299 | Three-dimensional ferroelectric memory device and method of making thereof | Yangyin Chen | 2018-04-10 |
| 9941331 | Device with sub-minimum pitch and method of making | Jordan Asher Katine, Yangyin Chen | 2018-04-10 |
| 9922709 | Memory hole bit line structures | Perumal Ratnam, Tianhong Yan | 2018-03-20 |
| 9859337 | Three-dimensional memory device with vertical semiconductor bit lines located in recesses and method of making thereof | Perumal Ratnam, Abhijit Bandyopadhyay | 2018-01-02 |
| 9837153 | Selecting reversible resistance memory cells based on initial resistance switching | Bijesh Rajamohanan, Xinde Hu | 2017-12-05 |
| 9818801 | Resistive three-dimensional memory device with heterostructure semiconductor local bit line and method of making thereof | Peter Rabkin, Perumal Ratnam, Masaaki Higashitani | 2017-11-14 |
| 9754665 | Vacancy-modulated conductive oxide resistive RAM device including an interfacial oxygen source layer | Yangyin Chen, Kun Hou | 2017-09-05 |