Issued Patents All Time
Showing 51–68 of 68 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7678665 | Deep STI trench and SOI undercut enabling STI oxide stressor | Michael D. Turner, Kurt H. Junker | 2010-03-16 |
| 7456055 | Process for forming an electronic device including semiconductor fins | Marius Orlowski | 2008-11-25 |
| 7288448 | Method and apparatus for mobility enhancement in a semiconductor device | Marius Orlowski | 2007-10-30 |
| 7078297 | Memory with recessed devices | James D. Burnett | 2006-07-18 |
| 6713381 | Method of forming semiconductor device including interconnect barrier layers | Alexander L. Barr, David B. Clegg, Rebecca G. Cole, Olubunmi O. Adetutu, Stuart E. Greer +5 more | 2004-03-30 |
| 6573173 | Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process | János Farkas, Brian G. Anthony, Abbas Guvenilir, Mohammed Rabiul Islam, Venkat R. Kolagunta +2 more | 2003-06-03 |
| 6551919 | Method for forming a dual inlaid copper interconnect structure | Bradley P. Smith, Mohammed Rabiul Islam | 2003-04-22 |
| 6444569 | Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process | János Farkas, Brian G. Anthony, Abbas Guvenilir, Mohammed Rabiul Islam, Venkat R. Kolagunta +2 more | 2002-09-03 |
| 6362057 | Method for forming a semiconductor device | William J. Taylor, Jr., Asanga H. Perera | 2002-03-26 |
| 6326301 | Method for forming a dual inlaid copper interconnect structure | Bradley P. Smith, Mohammed Rabiul Islam | 2001-12-04 |
| 6274478 | Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process | János Farkas, Brian G. Anthony, Abbas Guvenilir, Mohammed Rabiul Islam, Venkat R. Kolagunta +2 more | 2001-08-14 |
| 5960270 | Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions | Veena Misra, Christopher C. Hobbs, Brad Smith, Jeffrey S. Cope, Earnest B. Wilson | 1999-09-28 |
| 5736435 | Process for fabricating a fully self-aligned soi mosfet | Stephen S. Poon, Jeffrey W. Lutze, Sergio A. Ajuria | 1998-04-07 |
| 5627097 | Method for making CMOS device having reduced parasitic capacitance | Stephen S. Poon, Jeffrey W. Lutze | 1997-05-06 |
| 5554870 | Integrated circuit having both vertical and horizontal devices and process for making the same | Jon T. Fitch, Keith E. Witek | 1996-09-10 |
| 5459096 | Process for fabricating a semiconductor device using dual planarization layers | Stephen S. Poon | 1995-10-17 |
| 5349228 | Dual-gated semiconductor-on-insulator field effect transistor | Gerold W. Neudeck | 1994-09-20 |
| 5273921 | Methods for fabricating a dual-gated semiconductor-on-insulator field effect transistor | Gerold W. Neudeck | 1993-12-28 |