Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication

Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication

US Patent 6764949 · Granted Jul 20, 2004

Estimated economic value: $1,607,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Method of spacer formation with straight sidewall of memory cells2025
High-voltage devices integrated on semiconductor-on-insulator substrate2023
Memory device with density-controllable dummy fill strategy for near-MRAM perip2021
System and method for manufacturing self-aligned STI with single poly2020
Split-gate semiconductor device with L-shaped gate2020
Density-controllable dummy fill strategy for near-MRAM periphery and far-outside2019
Split-gate semiconductor device with L-shaped gate2018
Integrated circuits and methods for fabricating integrated circuits with non-vol2017
Integrated circuits with flash memory and methods for producing the same2017
Ion implantation-assisted etch-back process for improving spacer shape and space2017
Magnetism-controllable dummy structures in memory device2017
Buried hard mask for embedded semiconductor device patterning2017