Issued Patents All Time
Showing 26–50 of 88 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9417855 | Instruction and logic to perform dynamic binary translation | Abhay S. Kanhere, Koichi Yamada, Suriya Madras-Subramanian, Suresh Srinivas | 2016-08-16 |
| 9411739 | System, method and apparatus for improving transactional memory (TM) throughput using TM region indicators | Omar M. Shaikh, Ravi Rajwar, Muawya M. Al-Otoom | 2016-08-09 |
| 9342284 | Optimization of instructions to reduce memory access violations | Wessam M. Hassanein, Abhay S. Kanhere | 2016-05-17 |
| 9330020 | System, apparatus, and method for transparent page level instruction translation | Vedvyas Shanbhogue, Koichi Yamada | 2016-05-03 |
| 9292294 | Detection of memory address aliasing and violations of data dependency relationships | Muawya M. Al-Otoom, Ryan Carlson, Ho-Seop Kim, Omar M. Shaikh | 2016-03-22 |
| 9280492 | System and method for a load instruction with code conversion having access permissions to indicate failure of load content from registers | Alexandre J. Farcy | 2016-03-08 |
| 9256438 | Mechanism for increasing the effective capacity of the working register file | Shailender Chaudhry, Marc Tremblay | 2016-02-09 |
| 9146744 | Store queue having restricted and unrestricted entries | Martin Karlsson, Shailender Chaudhry, Gideon N. Levinsky | 2015-09-29 |
| 9032381 | State recovery methods and apparatus for computing platforms | Abhay S. Kanhere, Saurabh Shukla, Suriya Subramanian | 2015-05-12 |
| 8826257 | Memory disambiguation hardware to support software binary translation | Muawya M. Al-Otoom, Abhay S. Kanhere, Arvind Krishnaswamy, Omar M. Shaikh | 2014-09-02 |
| 8732438 | Anti-prefetch instruction | Sherman H. Yip, Gideon N. Levinsky | 2014-05-20 |
| 8572356 | Space-efficient mechanism to support additional scouting in a processor using checkpoints | Sherman H. Yip | 2013-10-29 |
| 8484434 | Index generation for cache memories | Martin Karlsson, Shailender Chaudhry | 2013-07-09 |
| 8447931 | Processor with a register file that supports multiple-issue execution | Shailender Chaudhry, Marc Tremblay | 2013-05-21 |
| 8364900 | Pseudo-LRU cache line replacement for a high-speed cache | Sherman H. Yip, Shailender Chaudhry | 2013-01-29 |
| 8316366 | Facilitating transactional execution in a processor that supports simultaneous speculative threading | Sherman H. Yip, Marc Tremblay | 2012-11-20 |
| 8185692 | Unified cache structure that facilitates accessing translation table entries | Gregory M. Wright | 2012-05-22 |
| 8181002 | Merging checkpoints in an execute-ahead processor | Sherman H. Yip, Marc Tremblay | 2012-05-15 |
| 8161273 | Method and apparatus for programmatically rewinding a register inside a transaction | — | 2012-04-17 |
| 8151084 | Using address and non-address information for improved index generation for cache memories | Martin Karlsson, Shailender Chaudhry | 2012-04-03 |
| 8065485 | Method and apparatus for determining cache storage locations based on latency requirements | Gideon N. Levinsky, Sherman H. Yip | 2011-11-22 |
| 8041900 | Method and apparatus for improving transactional memory commit latency | Martin Karlsson, Sherman H. Yip | 2011-10-18 |
| 7934080 | Aggressive store merging in a processor that supports checkpointing | Martin Karlsson, Gideon N. Levinsky, Khondakar A. Mujtaba, Shailender Chaudhry, Murali K. Inaganti | 2011-04-26 |
| 7930695 | Method and apparatus for synchronizing threads on a processor that supports transactional memory | Shailender Chaudhry, Marc Tremblay | 2011-04-19 |
| 7890739 | Method and apparatus for recovering from branch misprediction | — | 2011-02-15 |