Issued Patents All Time
Showing 76–88 of 88 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7395418 | Using a transactional execution mechanism to free up processor resources used by a busy-waiting thread | Wayne Mesard | 2008-07-01 |
| 7353363 | Patchable and/or programmable decode using predecode selection | Shailender Chaudhry, Quinn A. Jacobson, Marc Tremblay | 2008-04-01 |
| 7331039 | Method for graphically displaying hardware performance simulators | Sherman H. Yip | 2008-02-12 |
| 7293163 | Method and apparatus for dynamically adjusting the aggressiveness of an execute-ahead processor to hide memory latency | Sherman H. Yip | 2007-11-06 |
| 7293160 | Mechanism for eliminating the restart penalty when reissuing deferred instructions | Shailender Chaudhry, Marc Tremblay | 2007-11-06 |
| 7293161 | Deferring loads and stores when a load buffer or store buffer fills during execute-ahead mode | Shailender Chaudhry, Marc Tremblay | 2007-11-06 |
| 7277989 | Selectively performing fetches for store operations during speculative execution | Shailender Chaudhry, Marc Tremblay | 2007-10-02 |
| 7263603 | Method and apparatus for avoiding read-after-write hazards in an execute-ahead processor | Shailender Chaudhry, Marc Tremblay | 2007-08-28 |
| 7257700 | Avoiding register RAW hazards when returning from speculative execution | Shailender Chaudhry, Sherman H. Yip, Marc Tremblay | 2007-08-14 |
| 7257699 | Selective execution of deferred instructions in a processor that supports speculative execution | Shailender Chaudhry, Marc Tremblay | 2007-08-14 |
| 7216219 | Method and apparatus for avoiding write-after-read hazards in an execute-ahead processor | Shailender Chaudhry, Marc Tremblay | 2007-05-08 |
| 7213133 | Method and apparatus for avoiding write-after-write hazards in an execute-ahead processor | Shailender Chaudhry | 2007-05-01 |
| 7020748 | Cache replacement policy to mitigate pollution in multicore processors | — | 2006-03-28 |