Issued Patents All Time
Showing 51–75 of 88 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7836290 | Return address stack recovery in a speculative execution computing apparatus | Shailender Chaudhry, Quinn A. Jacobson, Marc Tremblay | 2010-11-16 |
| 7757068 | Method and apparatus for measuring performance during speculative execution | Shailender Chaudhry, Sherman H. Yip | 2010-07-13 |
| 7716457 | Method and apparatus for counting instructions during speculative execution | Shailender Chaudhry, Sherman H. Yip | 2010-05-11 |
| 7707359 | Method and apparatus for selectively prefetching based on resource availability | Wayne Mesard | 2010-04-27 |
| 7689813 | Method and apparatus for enforcing membar instruction semantics in an execute-ahead processor | Shailender Chaudhry, Marc Tremblay | 2010-03-30 |
| 7650487 | Method and structure for coordinating instruction execution in out-of-order processor execution using an instruction including an artificial register dependency | Shailender Chaudhry, Sherman H. Yip | 2010-01-19 |
| 7647477 | Branch target aware instruction prefetching technique | Shailender Chaudhry | 2010-01-12 |
| 7634641 | Method and apparatus for using multiple threads to spectulatively execute instructions | Shailender Chaudhry, Marc Tremblay | 2009-12-15 |
| 7634639 | Avoiding live-lock in a processor that supports speculative execution | Shailender Chaudhry, Sherman H. Yip, Guarav Garg, Ketaki Rao | 2009-12-15 |
| 7617421 | Method and apparatus for reporting failure conditions during transactional execution | Sherman H. Yip, Shailender Chaudhry | 2009-11-10 |
| 7610470 | Preventing register data flow hazards in an SST processor | Shailender Chaudhry, Marc Tremblay | 2009-10-27 |
| 7610474 | Mechanism for hardware tracking of return address after tail call elimination of return-type instruction | Sherman H. Yip, Shailender Chaudhry | 2009-10-27 |
| 7590830 | Method and structure for concurrent branch prediction in a processor | Shailender Chaudhry | 2009-09-15 |
| 7584346 | Method and apparatus for supporting different modes of multi-threaded speculative execution | Shailender Chaudhry, Marc Tremblay | 2009-09-01 |
| 7571304 | Generation of multiple checkpoints in a processor that supports speculative execution | Shailender Chaudhry, Marc Tremblay | 2009-08-04 |
| 7509481 | Patchable and/or programmable pre-decode | Shailender Chaudhry, Quinn A. Jacobson, Marc Tremblay | 2009-03-24 |
| 7509472 | Collapsible front-end translation for instruction fetch | Shailender Chaudhry | 2009-03-24 |
| 7484080 | Entering scout-mode when stores encountered during execute-ahead mode exceed the capacity of the store buffer | Shailender Chaudhry, Marc Tremblay | 2009-01-27 |
| 7480787 | Method and structure for pipelining of SIMD conditional moves | Lawrence Spracklen, Sherman H. Yip | 2009-01-20 |
| 7478203 | Technique for eliminating dead stores in a processor | Shailender Chaudhry | 2009-01-13 |
| 7472264 | Predicting a jump target based on a program counter and state information for a process | Edmond H. Yip, Shailender Chaudhry, Jiejun Lu | 2008-12-30 |
| 7461208 | Circuitry and method for accessing an associative cache with parallel determination of data and data availability | Sherman H. Yip, Shailender Chaudhry | 2008-12-02 |
| 7461237 | Method and apparatus for suppressing duplicative prefetches for branch target cache lines | Abid Ali, Shailender Chaudhry, Miles Lee | 2008-12-02 |
| 7421465 | Arithmetic early bypass | Leonard Rarick, Murali K. Inaganti, Shailender Chaudhry | 2008-09-02 |
| 7418581 | Method and apparatus for sampling instructions on a processor that supports speculative execution | Shailender Chaudhry, Sherman H. Yip | 2008-08-26 |