Issued Patents All Time
Showing 51–75 of 170 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6867500 | Multi-chip module and methods | David J. Corisis, Matt E. Schwab | 2005-03-15 |
| 6837731 | Locking assembly for securing a semiconductor device to a carrier substrate | David J. Corisis, Terry R. Lee | 2005-01-04 |
| 6831353 | Interdigitated leads-over-chip lead frame and device for supporting an integrated circuit die | Aaron Schoenfeld | 2004-12-14 |
| 6815251 | High density modularity for IC's | Salman Akram | 2004-11-09 |
| 6781839 | Vertical surface mount apparatus with thermal carrier and method | Larry D. Kinsman, Walter L. Moden | 2004-08-24 |
| 6773955 | Low profile multi-IC chip package connector | Walter L. Moden, Jerrold L. King | 2004-08-10 |
| 6747344 | Lead frame assemblies with voltage reference plane and IC packages including same | David J. Corisis, Terry R. Lee | 2004-06-08 |
| 6740971 | Cavity ball grid array apparatus having improved inductance characteristics | Steven G. Thummel | 2004-05-25 |
| 6738263 | Stackable ball grid array package | David J. Corisis, Walter L. Moden | 2004-05-18 |
| 6737734 | Structure and method for securing bussing leads | Larry D. Kinsman, Timothy J. Allen | 2004-05-18 |
| 6686655 | Low profile multi-IC chip package connector | Walter L. Moden, Jerrold L. King | 2004-02-03 |
| 6677671 | Apparatus for forming a stack of packaged memory dice | Jerrold L. King | 2004-01-13 |
| 6670702 | Stackable ball grid array package | David J. Corisis, Walter L. Moden | 2003-12-30 |
| 6656767 | Method of forming a stack of packaged memory dice | Jerrold L. King | 2003-12-02 |
| 6648663 | Locking assembly for securing semiconductor device to carrier substrate | David J. Corisis, Terry R. Lee | 2003-11-18 |
| 6635954 | Stress reduction feature for LOC lead frame | Larry D. Kinsman, Timothy J. Allen | 2003-10-21 |
| 6630733 | Integrated circuit package electrical enhancement | David J. Corisis | 2003-10-07 |
| 6617198 | Semiconductor assembly without adhesive fillets | — | 2003-09-09 |
| 6610162 | Methods for stress reduction feature for LOC lead frame | Larry D. Kinsman, Timothy J. Allen | 2003-08-26 |
| 6611058 | Vertical surface mount assembly and methods | Larry D. Kinsman, Warren M. Farnworth, Walter L. Moden, Terry R. Lee | 2003-08-26 |
| 6603198 | Semiconductor structure having stacked semiconductor devices | Salman Akram | 2003-08-05 |
| 6590277 | Reduced stress LOC assembly | Jerrold L. King, Larry D. Kinsman, David J. Corisis | 2003-07-08 |
| 6583503 | Semiconductor package with stacked substrates and multiple semiconductor dice | Salman Akram | 2003-06-24 |
| 6577503 | Vertical surface mount apparatus with thermal carrier | Larry D. Kinsman, Walter L. Moden | 2003-06-10 |
| 6576987 | Interdigitated leads-over-chip lead frame, device, and method for supporting an integrated circuit die | Aaron Schoenfeld | 2003-06-10 |