Issued Patents All Time
Showing 101–125 of 176 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7058920 | Methods for designing PLD architectures for flexible placement of IP function blocks | Andy L. Lee, Cameron McClintock, Richard G. Cliff, Srinivas T. Reddy, Chris Lane +3 more | 2006-06-06 |
| 7057967 | Multi-mode synchronous memory device and methods of operating and testing same | Brent Keeth, Jeffrey W. Janzen, Troy A. Manning, Chris G. Martin | 2006-06-06 |
| 7058799 | Apparatus and method for clock domain crossing with integrated decode | — | 2006-06-06 |
| 7051982 | Fairing arrangements for aircraft | — | 2006-05-30 |
| 7038966 | Memory device and method having data path with multiple prefetch I/O configurations | Brent Keeth, Troy A. Manning | 2006-05-02 |
| 7030674 | Multiphase clock generators | — | 2006-04-18 |
| 7031215 | Memory device and method having data path with multiple prefetch I/O configurations | Brent Keeth, Troy A. Manning | 2006-04-18 |
| 7027337 | Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency | Christopher Johnson | 2006-04-11 |
| 7013252 | Simulated circuit node initializing and monitoring | Bohr-Winn Shih, John S. Mullin | 2006-03-14 |
| 7000872 | Circular parachute | Nobuyuki Fujiwara | 2006-02-21 |
| 6970014 | Routing architecture for a programmable logic device | David Lewis, Paul Leventis, Andy L. Lee, Richard G. Cliff, Srinivas T. Reddy +5 more | 2005-11-29 |
| 6965249 | Programmable logic device with redundant circuitry | Christopher F. Lane, Ketan Zaveri, Hyun Yi, Giles V. Powell, Paul Leventis +7 more | 2005-11-15 |
| 6958236 | Control of gene expression in plants | Erica Pascal, Scott Valentine, Jeffrey A. Brown, Adam Cockrell | 2005-10-25 |
| 6934199 | Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency | Christopher Johnson | 2005-08-23 |
| 6930955 | Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM | Brent Keeth, Feng Lin | 2005-08-16 |
| 6909196 | Method and structures for reduced parasitic capacitance in integrated circuit metallizations | Shubneesh Batra, Michael Chaine, Brent Keeth, Salman Akram, Troy A. Manning +3 more | 2005-06-21 |
| 6894551 | Multiphase clock generators | — | 2005-05-17 |
| 6889357 | Timing calibration pattern for SLDRAM | Brent Keeth, Terry R. Lee, Paul Fuller | 2005-05-03 |
| 6882579 | Memory device and method having data path with multiple prefetch I/O configurations | Brent Keeth, Troy A. Manning | 2005-04-19 |
| 6876562 | Apparatus and method for mounting microelectronic devices on a mirrored board assembly | Chris G. Martin, Brent Keeth, Walter L. Moden | 2005-04-05 |
| 6859065 | Use of dangling partial lines for interfacing in a PLD | Andy L. Lee, Cameron McClintock, Giles V. Powell, Paul Leventis | 2005-02-22 |
| 6857043 | Shift register implementations of first-in/first-out memories utilizing a double increment gray code counter | Andy L. Lee, Richard G. Cliff | 2005-02-15 |
| 6851016 | System latency levelization for read data | Jeffery W. Janzen, Brent Keeth, Kevin J. Ryan, Troy A. Manning | 2005-02-01 |
| 6842398 | Multi-mode synchronous memory device and methods of operating and testing same | Brent Keeth, Jeffrey W. Janzen, Troy A. Manning, Chris G. Martin | 2005-01-11 |
| 6836166 | Method and system for delay control in synchronization circuits | Feng Lin, Brent Keeth | 2004-12-28 |