Issued Patents All Time
Showing 76–100 of 176 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7310276 | Memory device and method having data path with multiple prefetch I/O configurations | Brent Keeth, Troy A. Manning | 2007-12-18 |
| 7287189 | I/O configuration and reconfiguration trigger through testing interface | Keith Duwel, Mario Guzman, Christopher F. Lane, Andy L. Lee | 2007-10-23 |
| 7276949 | Multiphase clock generation | — | 2007-10-02 |
| 7269094 | Memory system and method for strobing data, command and address signals | Feng Lin, Brent Keeth, Seong-Hoon Lee | 2007-09-11 |
| 7254067 | Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency | Christopher Johnson | 2007-08-07 |
| 7251194 | Memory system and method for strobing data, command and address signals | Feng Lin, Brent Keeth, Seong-Hoon Lee | 2007-07-31 |
| 7245553 | Memory system and method for strobing data, command and address signals | Feng Lin, Brent Keeth, Seong-Hoon Lee | 2007-07-17 |
| 7234069 | Precise phase shifting using a DLL controlled, multi-stage delay chain | — | 2007-06-19 |
| 7227395 | High-performance memory interface circuit architecture | Joseph Huang, Chiakang Sung, Philip Pan, Yan Chong, Andy L. Lee | 2007-06-05 |
| 7200022 | Apparatus and method for mounting microelectronic devices on a mirrored board assembly | Chris G. Martin, Brent Keeth, Walter L. Moden | 2007-04-03 |
| 7196542 | Techniques for providing increased flexibility to input/output banks with respect to supply voltages | Andy L. Lee, Toan Thanh Nguyen, Stephanie Tran, Cameron McClintock | 2007-03-27 |
| 7187617 | Memory system and method for strobing data, command and address signals | Feng Lin, Brent Keeth, Seong-Hoon Lee | 2007-03-06 |
| 7176714 | Multiple data rate memory interface architecture | Andy L. Lee | 2007-02-13 |
| 7173340 | Daisy chaining of serial I/O interface on stacking devices | Binling Zhou, James L. Todsen | 2007-02-06 |
| 7160795 | Method and structures for reduced parasitic capacitance in integrated circuit metallizations | Shubneesh Batra, Michael Chaine, Brent Keeth, Salman Akram, Troy A. Manning +3 more | 2007-01-09 |
| 7161821 | Apparatus and method for mounting microelectronic devices on a mirrored board assembly | Chris G. Martin, Brent Keeth, Walter L. Moden | 2007-01-09 |
| 7159092 | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same | Ronnie M. Harrison | 2007-01-02 |
| 7151707 | Memory device and method having data path with multiple prefetch I/O configurations | Brent Keeth, Troy A. Manning | 2006-12-19 |
| 7149141 | Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency | Christopher Johnson | 2006-12-12 |
| 7129738 | Method and apparatus for calibrating driver impedance | Feng Lin | 2006-10-31 |
| 7126874 | Memory system and method for strobing data, command and address signals | Feng Lin, Brent Keeth, Seong-Hoon Lee | 2006-10-24 |
| 7123051 | Soft core control of dedicated memory interface hardware in a programmable logic device | Andy L. Lee | 2006-10-17 |
| 7119574 | Passage structures for use in low-voltage applications | Andy L. Lee, Wanli Chang, Cameron McClintock, John E. Turner, Chiao Kai Hwang +2 more | 2006-10-10 |
| 7085880 | Method and apparatus for address FIFO for high-bandwidth command/address busses in digital storage system | — | 2006-08-01 |
| D525282 | Point of sale unit having integral customer and operator interfaces | Ray S. Barnes, James David Branck, Louis A. Brown, Gregory C. Cortese, Karen Sammon | 2006-07-18 |