Issued Patents All Time
Showing 25 most recent of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8565008 | Method and apparatus for generating a sequence of clock signals | — | 2013-10-22 |
| 8433023 | Method and apparatus for generating a phase dependent control signal | — | 2013-04-30 |
| 8107580 | Method and apparatus for generating a phase dependent control signal | — | 2012-01-31 |
| 7889593 | Method and apparatus for generating a sequence of clock signals | — | 2011-02-15 |
| 7746959 | Method and system for generating reference voltages for signal receivers | Brent Keeth, Joo S. Choi, George E. Pax, David K. Ovard, Dragos Dimitriu +4 more | 2010-06-29 |
| 7602876 | Method and apparatus for generating a phase dependent control signal | — | 2009-10-13 |
| 7577212 | Method and system for generating reference voltages for signal receivers | Brent Keeth, Joo S. Choi, George E. Pax, David K. Ovard, Dragos Dimitriu +4 more | 2009-08-18 |
| 7418071 | Method and apparatus for generating a phase dependent control signal | — | 2008-08-26 |
| 7415404 | Method and apparatus for generating a sequence of clock signals | — | 2008-08-19 |
| 7159092 | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same | Brian Johnson | 2007-01-02 |
| 7145376 | Method and circuitry for reducing duty cycle distortion in differential delay lines | Brent Keeth | 2006-12-05 |
| 7082678 | Method of fabricating an integrated circuit package | David J. Corisis | 2006-08-01 |
| 7055241 | Method of fabricating an integrated circuit package | David J. Corisis | 2006-06-06 |
| 7042265 | Interlaced delay-locked loops for controlling memory-circuit timing | — | 2006-05-09 |
| 7016451 | Method and apparatus for generating a phase dependent control signal | — | 2006-03-21 |
| 6954097 | Method and apparatus for generating a sequence of clock signals | — | 2005-10-11 |
| 6952462 | Method and apparatus for generating a phase dependent control signal | — | 2005-10-04 |
| 6931086 | Method and apparatus for generating a phase dependent control signal | — | 2005-08-16 |
| 6911807 | Method and circuit for limiting a pumped voltage | — | 2005-06-28 |
| 6842399 | Delay lock loop circuit useful in a synchronous system and associated methods | — | 2005-01-11 |
| 6806754 | Method and circuitry for reducing duty cycle distortion in differential delay lines | Brent Keeth | 2004-10-19 |
| 6801989 | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same | Brian Johnson | 2004-10-05 |
| 6781419 | Method and system for controlling the duty cycle of a clock signal | — | 2004-08-24 |
| 6777995 | Interlaced delay-locked loops for controlling memory-circuit timing | — | 2004-08-17 |
| 6753675 | Method and circuit for limiting a pumped voltage | — | 2004-06-22 |