Issued Patents All Time
Showing 126–150 of 176 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6826741 | Flexible I/O routing resources | Andy L. Lee, Cameron McClintock, Triet Nguyen, David Jefferson, Paul Leventis +3 more | 2004-11-30 |
| 6807500 | Method and apparatus providing improved data path calibration for memory devices | Brent Keeth | 2004-10-19 |
| 6807613 | Synchronized write data on a high speed memory bus | Brent Keeth | 2004-10-19 |
| 6801989 | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same | Ronnie M. Harrison | 2004-10-05 |
| 6762974 | Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM | Brent Keeth, Feng Lin | 2004-07-13 |
| 6751717 | Method and apparatus for clock synchronization between a system clock and a burst data clock | — | 2004-06-15 |
| 6732223 | Method and apparatus for address FIFO for high-bandwidth command/address busses in digital storage system | — | 2004-05-04 |
| 6697297 | Apparatus for setting write latency | Brent Keeth | 2004-02-24 |
| 6697926 | Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device | Brent Keeth, Troy A. Manning | 2004-02-24 |
| 6693836 | Memory device and method having data path with multiple prefetch I/O configurations | Brent Keeth, Troy A. Manning | 2004-02-17 |
| 6690609 | Memory device and method having data path with multiple prefetch I/O configurations | Brent Keeth, Troy A. Manning | 2004-02-10 |
| 6687185 | Method and apparatus for setting and compensating read latency in a high speed DRAM | Brent Keeth, Feng Lin | 2004-02-03 |
| 6683814 | Memory device and method having data path with multiple prefetch I/O configurations | Brent Keeth, Troy A. Manning | 2004-01-27 |
| 6678205 | Multi-mode synchronous memory device and method of operating and testing same | Brent Keeth, Jeffrey W. Janzen, Troy A. Manning, Chris G. Martin | 2004-01-13 |
| 6674378 | Predictive timing calibration for memory devices | Brent Keeth | 2004-01-06 |
| 6665223 | Memory device and method having data path with multiple prefetch I/O configurations | Brent Keeth, Troy A. Manning | 2003-12-16 |
| 6661253 | Passgate structures for use in low-voltage applications | Andy L. Lee, Wanli Chang, Cameron McClintock, John E. Turner, Chiao Kai Hwang +2 more | 2003-12-09 |
| 6658523 | System latency levelization for read data | Jeffery W. Janzen, Brent Keeth, Kevin J. Ryan, Troy A. Manning | 2003-12-02 |
| 6653862 | Use of dangling partial lines for interfacing in a PLD | Andy L. Lee, Cameron McClintock, Giles V. Powell, Paul Leventis | 2003-11-25 |
| 6630842 | Routing architecture for a programmable logic device | David Lewis, Paul Leventis, Andy L. Lee, Richard G. Cliff, Srinivas T. Reddy +5 more | 2003-10-07 |
| 6605962 | PLD architecture for flexible placement of IP function blocks | Andy L. Lee, Cameron McClintock, Richard G. Cliff, Srinivas T. Reddy, Chris Lane +3 more | 2003-08-12 |
| 6606041 | Predictive timing calibration for memory devices | Brent Keeth | 2003-08-12 |
| 6605970 | Method and apparatus for crossing from an unstable to a stable clock domain in a memory device | Brent Keeth | 2003-08-12 |
| 6587804 | Method and apparatus providing improved data path calibration for memory devices | Brent Keeth | 2003-07-01 |
| 6522172 | High speed latch/register | Brent Keeth | 2003-02-18 |