Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10043716 | N-well/P-well strap structures | Dustin Do, Andy L. Lee, Bradley Jensen, Swee Aun Lau, Wuu-Cherng Lin +1 more | 2018-08-07 |
| 9904756 | Methods, systems, and computer program product for implementing DRC clean multi-patterning process nodes with lateral fills in electronic designs | Roland Ruehl, Alexandre Arkhipov, Karun Sharma | 2018-02-27 |
| 9659138 | Methods, systems, and computer program product for a bottom-up electronic design implementation flow and track pattern definition for multiple-patterning lithographic techniques | Alexandre Arkhipov, Roland Ruehl, Karun Sharma | 2017-05-23 |
| 9652579 | Methods, systems, and computer program product for implementing DRC clean multi-patterning process nodes with parallel fills in electronic designs | Alexandre Arkhipov, Roland Ruehl, Karun Sharma | 2017-05-16 |
| 9449962 | N-well/P-well strap structures | Dustin Do, Andy L. Lee, Bradley Jensen, Swee Aun Lau, Wuu-Cherng Lin +1 more | 2016-09-20 |
| 9219483 | Integrated circuit floorplans | Christopher F. Lane, Jeffrey Tyhach | 2015-12-22 |
| 8835224 | Distributing power with through-silicon-vias | Thomas H. White, Rakesh Patel | 2014-09-16 |
| 8344496 | Distributing power with through-silicon-vias | Thomas H. White, Rakesh Patel | 2013-01-01 |
| 8217464 | N-well/P-well strap structures | Dustin Do, Andy L. Lee, Bradley Jensen, Swee Aun Lau, Wuu-Cherng Lin +1 more | 2012-07-10 |
| 6965249 | Programmable logic device with redundant circuitry | Christopher F. Lane, Ketan Zaveri, Hyun Yi, Paul Leventis, David Jefferson +7 more | 2005-11-15 |
| 6859065 | Use of dangling partial lines for interfacing in a PLD | Brian Johnson, Andy L. Lee, Cameron McClintock, Paul Leventis | 2005-02-22 |
| 6670825 | Efficient arrangement of interconnection resources on programmable logic devices | Christopher F. Lane, Wayne Yeung, Chiakang Sung, Bruce B. Pedersen | 2003-12-30 |
| 6653862 | Use of dangling partial lines for interfacing in a PLD | Brian Johnson, Andy L. Lee, Cameron McClintock, Paul Leventis | 2003-11-25 |
| 6507216 | Efficient arrangement of interconnection resources on programmable logic devices | Christopher F. Lane, Wayne Yeung, Chiakang Sung, Bruce B. Pedersen | 2003-01-14 |