Issued Patents All Time
Showing 151–175 of 332 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6934173 | 256 Meg dynamic random access memory | Layne Bunker, Scott J. Derner | 2005-08-23 |
| 6930955 | Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM | Brian Johnson, Feng Lin | 2005-08-16 |
| 6912680 | Memory system with dynamic timing correction | — | 2005-06-28 |
| 6909196 | Method and structures for reduced parasitic capacitance in integrated circuit metallizations | Shubneesh Batra, Michael Chaine, Salman Akram, Troy A. Manning, Brian Johnson +3 more | 2005-06-21 |
| 6900493 | Semiconductor memory circuitry | Pierre C. Fazan | 2005-05-31 |
| 6898102 | Digitline architecture for dynamic memory | — | 2005-05-24 |
| 6889357 | Timing calibration pattern for SLDRAM | Brian Johnson, Terry R. Lee, Paul Fuller | 2005-05-03 |
| 6882579 | Memory device and method having data path with multiple prefetch I/O configurations | Brian Johnson, Troy A. Manning | 2005-04-19 |
| 6876562 | Apparatus and method for mounting microelectronic devices on a mirrored board assembly | Chris G. Martin, Brian Johnson, Walter L. Moden | 2005-04-05 |
| 6862654 | Method and system for using dynamic random access memory as cache memory | Brian M. Shirley, Charles H. Dennison, Kevin J. Ryan | 2005-03-01 |
| 6851016 | System latency levelization for read data | Jeffery W. Janzen, Kevin J. Ryan, Troy A. Manning, Brian Johnson | 2005-02-01 |
| 6850452 | 256 Meg dynamic random access memory | Layne Bunker | 2005-02-01 |
| 6847583 | Method of synchronizing read timing in a high speed memory system | Jeffery W. Janzen, Troy A. Manning, Chris G. Martin | 2005-01-25 |
| 6847100 | High speed IC package configuration | David J. Corisis | 2005-01-25 |
| 6842398 | Multi-mode synchronous memory device and methods of operating and testing same | Brian Johnson, Jeffrey W. Janzen, Troy A. Manning, Chris G. Martin | 2005-01-11 |
| 6842393 | Method for selecting one or a bank of memory devices | Kevin J. Ryan | 2005-01-11 |
| 6839265 | Bi-level digit line architecture for high density DRAMS | — | 2005-01-04 |
| 6836166 | Method and system for delay control in synchronization circuits | Feng Lin, Brian Johnson | 2004-12-28 |
| 6819611 | Method and apparatus for data compression in memory devices | — | 2004-11-16 |
| 6807613 | Synchronized write data on a high speed memory bus | Brian Johnson | 2004-10-19 |
| 6806754 | Method and circuitry for reducing duty cycle distortion in differential delay lines | Ronnie M. Harrison | 2004-10-19 |
| 6807114 | Method and system for selecting redundant rows and columns of memory cells | Troy A. Manning, Chris G. Martin, Ebrahim H. Hargan | 2004-10-19 |
| 6807500 | Method and apparatus providing improved data path calibration for memory devices | Brian Johnson | 2004-10-19 |
| 6790732 | Self-aligned dual-gate transistor device and method of forming self-aligned dual-gate transistor device | John K. Zahurak, Charles H. Dennison | 2004-09-14 |
| 6762974 | Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM | Brian Johnson, Feng Lin | 2004-07-13 |