Issued Patents All Time
Showing 126–150 of 332 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7200022 | Apparatus and method for mounting microelectronic devices on a mirrored board assembly | Chris G. Martin, Brian Johnson, Walter L. Moden | 2007-04-03 |
| 7190625 | Method and apparatus for data compression in memory devices | — | 2007-03-13 |
| 7187617 | Memory system and method for strobing data, command and address signals | Feng Lin, Brian Johnson, Seong-Hoon Lee | 2007-03-06 |
| 7161821 | Apparatus and method for mounting microelectronic devices on a mirrored board assembly | Chris G. Martin, Brian Johnson, Walter L. Moden | 2007-01-09 |
| 7160795 | Method and structures for reduced parasitic capacitance in integrated circuit metallizations | Shubneesh Batra, Michael Chaine, Salman Akram, Troy A. Manning, Brian Johnson +3 more | 2007-01-09 |
| 7155561 | Method and system for using dynamic random access memory as cache memory | Brian M. Shirley, Charles H. Dennison | 2006-12-26 |
| 7151707 | Memory device and method having data path with multiple prefetch I/O configurations | Brian Johnson, Troy A. Manning | 2006-12-19 |
| 7145376 | Method and circuitry for reducing duty cycle distortion in differential delay lines | Ronnie M. Harrison | 2006-12-05 |
| 7136316 | Method and apparatus for data compression in memory devices | — | 2006-11-14 |
| 7126874 | Memory system and method for strobing data, command and address signals | Feng Lin, Brian Johnson, Seong-Hoon Lee | 2006-10-24 |
| 7123046 | Apparatus for adaptively adjusting a data receiver | — | 2006-10-17 |
| 7065001 | Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM | James B. Johnson, Feng Lin | 2006-06-20 |
| 7064036 | Dual-gate transistor device and method of forming a dual-gate transistor device | John K. Zahurak, Charles H. Dennison | 2006-06-20 |
| 7057967 | Multi-mode synchronous memory device and methods of operating and testing same | Brian Johnson, Jeffrey W. Janzen, Troy A. Manning, Chris G. Martin | 2006-06-06 |
| 7057225 | Semiconductor memory circuitry | Pierre C. Fazan | 2006-06-06 |
| 7054207 | Method and system for selecting redundant rows and columns of memory cells | Troy A. Manning, Chris G. Martin, Ebrahim H. Hargan | 2006-05-30 |
| 7038966 | Memory device and method having data path with multiple prefetch I/O configurations | Brian Johnson, Troy A. Manning | 2006-05-02 |
| 7031215 | Memory device and method having data path with multiple prefetch I/O configurations | Brian Johnson, Troy A. Manning | 2006-04-18 |
| 7027349 | Method for selecting memory device in response to bank selection signal | Kevin J. Ryan | 2006-04-11 |
| 7009232 | Semiconductor memory circuitry including die sites sized for 256M to 275M memory cells in an 8-inch wafer | Pierre C. Fazan | 2006-03-07 |
| 6999361 | Method and apparatus for data compression in memory devices | — | 2006-02-14 |
| 6987702 | Method and apparatus for data compression in memory devices | — | 2006-01-17 |
| 6967369 | Semiconductor memory circuitry | Pierre C. Fazan | 2005-11-22 |
| 6959016 | Method and apparatus for adjusting the timing of signals over fine and coarse ranges | Troy A. Manning | 2005-10-25 |
| 6948027 | Method and system for using dynamic random access memory as cache memory | Brian M. Shirley, Charles H. Dennison, Kevin J. Ryan | 2005-09-20 |