Issued Patents All Time
Showing 101–125 of 332 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7593286 | Write latency tracking using a delay lock loop in a synchronous DRAM | James B. Johnson, Feng Lin | 2009-09-22 |
| 7577212 | Method and system for generating reference voltages for signal receivers | Joo S. Choi, George E. Pax, Ronnie M. Harrison, David K. Ovard, Dragos Dimitriu +4 more | 2009-08-18 |
| 7549033 | Dual edge command | Joo S. Choi, Troy A. Manning | 2009-06-16 |
| 7521956 | Methods and apparatus for adaptively adjusting a data receiver | — | 2009-04-21 |
| 7492652 | Apparatus and method for repairing a semiconductor memory | Chris G. Martin, Troy A. Manning | 2009-02-17 |
| 7489564 | 256 Meg dynamic random access memory | Layne Bunker, Raymond J. Beffa, Frank F. Ross | 2009-02-10 |
| 7480203 | Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM | James B. Johnson, Feng Lin | 2009-01-20 |
| 7477556 | 256 Meg dynamic random access memory | Layne Bunker, Raymond J. Beffa, Frank F. Ross | 2009-01-13 |
| 7477557 | 256 Meg dynamic random access memory | Layne Bunker, Raymond J. Beffa, Frank F. Ross | 2009-01-13 |
| 7457172 | Memory device and method having data path with multiple prefetch I/O configurations | Brian Johnson, Troy A. Manning | 2008-11-25 |
| 7412634 | On-chip sampling circuit and method | Chris G. Martin, James B. Johnson, Troy A. Manning | 2008-08-12 |
| 7408825 | Apparatus and method for repairing a semiconductor memory | Chris G. Martin, Troy A. Manning | 2008-08-05 |
| 7404124 | On-chip sampling circuit and method | Chris G. Martin, James B. Johnson, Troy A. Manning | 2008-07-22 |
| 7355922 | Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM | James B. Johnson, Feng Lin | 2008-04-08 |
| 7355920 | Write latency tracking using a delay lock loop in a synchronous DRAM | James B. Johnson, Feng Lin | 2008-04-08 |
| 7350018 | Method and system for using dynamic random access memory as cache memory | Brian M. Shirley, Charles H. Dennison, Kevin J. Ryan | 2008-03-25 |
| 7336111 | Fast-locking digital phase locked loop | Feng Lin | 2008-02-26 |
| 7310276 | Memory device and method having data path with multiple prefetch I/O configurations | Brian Johnson, Troy A. Manning | 2007-12-18 |
| 7299329 | Dual edge command in DRAM | Joo S. Choi, Troy A. Manning | 2007-11-20 |
| 7269094 | Memory system and method for strobing data, command and address signals | Feng Lin, Brian Johnson, Seong-Hoon Lee | 2007-09-11 |
| 7251762 | On-chip sampling circuit and method | Chris G. Martin, James B. Johnson, Troy A. Manning | 2007-07-31 |
| 7251194 | Memory system and method for strobing data, command and address signals | Feng Lin, Brian Johnson, Seong-Hoon Lee | 2007-07-31 |
| 7245553 | Memory system and method for strobing data, command and address signals | Feng Lin, Brian Johnson, Seong-Hoon Lee | 2007-07-17 |
| 7221201 | Fast-locking digital phase locked loop | Feng Lin | 2007-05-22 |
| 7215586 | Apparatus and method for repairing a semiconductor memory | Chris G. Martin, Troy A. Manning | 2007-05-08 |