Issued Patents All Time
Showing 176–200 of 332 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6756836 | 256 Meg dynamic random access memory | Layne Bunker | 2004-06-29 |
| 6757200 | Semiconductor memory having dual port cell supporting hidden refresh | Charles H. Dennison | 2004-06-29 |
| 6750700 | 256 meg dynamic random access memory | Layne Bunker, Scott J. Derner | 2004-06-15 |
| 6741104 | DRAM sense amplifier for low voltages | Leonard Forbes | 2004-05-25 |
| 6735102 | 256 Meg dynamic random access memory | Layne Bunker, Larry D. Kinsman | 2004-05-11 |
| 6724666 | Method of synchronizing read timing in a high speed memory system | Jeffery W. Janzen, Troy A. Manning, Chris G. Martin | 2004-04-20 |
| 6710630 | 256 Meg dynamic random access memory | Layne Bunker | 2004-03-23 |
| 6710631 | 256 Meg dynamic random access memory | Layne Bunker, Scott J. Derner | 2004-03-23 |
| 6703656 | Semiconductor memory circuitry including die sites sized for 256M to 275M memory cells in a 12″ wafer | Pierre C. Fazan | 2004-03-09 |
| 6697297 | Apparatus for setting write latency | Brian Johnson | 2004-02-24 |
| 6696762 | Bi-level digit line architecture for high density DRAMS | — | 2004-02-24 |
| 6696867 | Voltage generator with stability indicator circuit | Layne Bunker, Scott J. Derner | 2004-02-24 |
| 6697926 | Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device | Brian Johnson, Troy A. Manning | 2004-02-24 |
| 6693836 | Memory device and method having data path with multiple prefetch I/O configurations | Brian Johnson, Troy A. Manning | 2004-02-17 |
| 6690609 | Memory device and method having data path with multiple prefetch I/O configurations | Brian Johnson, Troy A. Manning | 2004-02-10 |
| 6686786 | Voltage generator stability indicator circuit | Layne Bunker, Scott J. Derner | 2004-02-03 |
| 6687185 | Method and apparatus for setting and compensating read latency in a high speed DRAM | Brian Johnson, Feng Lin | 2004-02-03 |
| 6683814 | Memory device and method having data path with multiple prefetch I/O configurations | Brian Johnson, Troy A. Manning | 2004-01-27 |
| 6678205 | Multi-mode synchronous memory device and method of operating and testing same | Brian Johnson, Jeffrey W. Janzen, Troy A. Manning, Chris G. Martin | 2004-01-13 |
| 6674310 | 256 Meg dynamic random access memory | Layne Bunker, Scott J. Derner | 2004-01-06 |
| 6674378 | Predictive timing calibration for memory devices | Brian Johnson | 2004-01-06 |
| 6665223 | Memory device and method having data path with multiple prefetch I/O configurations | Brian Johnson, Troy A. Manning | 2003-12-16 |
| 6662304 | Method and apparatus for bit-to-bit timing correction of a high speed memory bus | Terry R. Lee, Kevin J. Ryan, Troy A. Manning | 2003-12-09 |
| 6661041 | Digitline architecture for dynamic memory | — | 2003-12-09 |
| 6658523 | System latency levelization for read data | Jeffery W. Janzen, Kevin J. Ryan, Troy A. Manning, Brian Johnson | 2003-12-02 |