Issued Patents All Time
Showing 226–250 of 332 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6452825 | 256 meg dynamic random access memory having a programmable multiplexor | Layne Bunker, Ronald Taylor, John S. Mullin | 2002-09-17 |
| 6445643 | Method and apparatus for setting write latency | Brian Johnson | 2002-09-03 |
| 6445636 | Method and system for hiding refreshes in a dynamic random access memory | Brian M. Shirley, Kevin J. Ryan, Charles H. Dennison | 2002-09-03 |
| 6445624 | Method of synchronizing read timing in a high speed memory system | Jeffery W. Janzen, Troy A. Manning, Chris G. Martin | 2002-09-03 |
| 6442084 | Semiconductor memory having segmented row repair | — | 2002-08-27 |
| 6442644 | Memory system having synchronous-link DRAM (SLDRAM) devices and controller | David Gustavson, David V. James, Hans A. Wiggers, Peter B. Gillingham, Cormac Michael O'Connell +9 more | 2002-08-27 |
| 6437600 | Adjustable output driver circuit | — | 2002-08-20 |
| 6438016 | Semiconductor memory having dual port cell supporting hidden refresh | Charles H. Dennison | 2002-08-20 |
| 6434081 | Calibration technique for memory devices | Brian Johnson | 2002-08-13 |
| 6429529 | Bi-level digit line architecture for high density drams | — | 2002-08-06 |
| 6430696 | Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same | — | 2002-08-06 |
| 6414378 | High speed IC package configuration | David J. Corisis | 2002-07-02 |
| 6414903 | Method and apparatus for crossing clock domain boundaries | Brian Johnson | 2002-07-02 |
| 6412052 | Method and apparatus for detecting an initialization signal and a command packet error in packetized dynamic random access memories | Troy A. Manning | 2002-06-25 |
| 6400595 | 256 meg dynamic access memory | Layne Bunker, Scott J. Derner | 2002-06-04 |
| 6392303 | Digit line architecture for dynamic memory | — | 2002-05-21 |
| 6374360 | Method and apparatus for bit-to-bit timing correction of a high speed memory bus | Terry R. Lee, Kevin J. Ryan, Troy A. Manning | 2002-04-16 |
| 6356498 | Selective power distribution circuit for an integrated circuit | — | 2002-03-12 |
| 6333893 | Method and apparatus for crossing clock domain boundaries | Brian Johnson | 2001-12-25 |
| 6326810 | Adjustable output driver circuit | — | 2001-12-04 |
| 6324088 | 256 meg dynamic random access memory | Layne Bunker, Raymond J. Beffa, Frank F. Ross | 2001-11-27 |
| 6316979 | Integrated circuit data latch driver circuit | — | 2001-11-13 |
| 6317358 | Efficient dual port DRAM cell using SOI technology | — | 2001-11-13 |
| 6314011 | 256 Meg dynamic random access memory | Layne Bunker, Ronald Taylor, John S. Mullin, Raymond J. Beffa, Frank F. Ross +1 more | 2001-11-06 |
| 6314030 | Semiconductor memory having segmented row repair | — | 2001-11-06 |