Issued Patents All Time
Showing 201–225 of 332 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6631084 | 256 Meg dynamic random access memory | Layne Bunker | 2003-10-07 |
| 6606041 | Predictive timing calibration for memory devices | Brian Johnson | 2003-08-12 |
| 6605970 | Method and apparatus for crossing from an unstable to a stable clock domain in a memory device | Brian Johnson | 2003-08-12 |
| 6600671 | Reduced area sense amplifier isolation layout in a dynamic RAM architecture | — | 2003-07-29 |
| 6597206 | 256 Meg dynamic random access memory | Layne Bunker, Scott J. Derner | 2003-07-22 |
| 6594173 | Method for digit line architecture for dynamic memory | — | 2003-07-15 |
| 6593192 | Method of forming a dual-gated semiconductor-on-insulator device | John K. Zahurak, Charles H. Dennison | 2003-07-15 |
| 6594168 | 256 Meg dynamic random access memory | Layne Bunker | 2003-07-15 |
| 6590795 | High speed data capture circuit for a digital device | Chris G. Martin | 2003-07-08 |
| 6587804 | Method and apparatus providing improved data path calibration for memory devices | Brian Johnson | 2003-07-01 |
| 6580158 | High speed IC package configuration | David J. Corisis | 2003-06-17 |
| 6580631 | 256 Meg dynamic random access memory | Layne Bunker, Scott J. Derner | 2003-06-17 |
| 6577523 | Reduced area sense amplifier isolation layout in a dynamic RAM architecture | — | 2003-06-10 |
| 6567288 | Methods for bi-level digit line architecture for high density DRAMS | — | 2003-05-20 |
| 6556065 | 256 Meg dynamic random access memory | Layne Bunker, Scott J. Derner | 2003-04-29 |
| 6538951 | Dram active termination control | Jeffery W. Janzen | 2003-03-25 |
| 6535450 | Method for selecting one or a bank of memory devices | Kevin J. Ryan | 2003-03-18 |
| 6522172 | High speed latch/register | Brian Johnson | 2003-02-18 |
| 6515914 | Memory device and method having data path with multiple prefetch I/O configurations | Brian Johnson, Troy A. Manning | 2003-02-04 |
| 6504255 | Digit line architecture for dynamic memory | — | 2003-01-07 |
| 6480031 | High speed latch/register | Brian Johnson | 2002-11-12 |
| 6480407 | Reduced area sense amplifier isolation layout in a dynamic RAM architecture | — | 2002-11-12 |
| 6477073 | 256 meg dynamic random access memory | Layne Bunker, Larry D. Kinsman | 2002-11-05 |
| 6465331 | DRAM fabricated on a silicon-on-insulator (SOI) substrate having bi-level digit lines | Charles H. Dennison | 2002-10-15 |
| 6456518 | Bi-level digit line architecture for high density drams | — | 2002-09-24 |