Issued Patents All Time
Showing 276–300 of 332 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6084434 | Adjustable output driver circuit | — | 2000-07-04 |
| 6084307 | Bi-level digit line architecture for high density DRAMS | — | 2000-07-04 |
| 6081463 | Semiconductor memory remapping | James M. Shaffer, Eugene H. Cloud, Salman Akram | 2000-06-27 |
| 6078540 | Selective power distribution circuit for an integrated circuit | — | 2000-06-20 |
| 6069504 | Adjustable output driver circuit having parallel pull-up and pull-down elements | — | 2000-05-30 |
| 6069510 | Low-skew differential signal converter | — | 2000-05-30 |
| 6057718 | Method and apparatus for a charge conserving driver circuit for capacitive loads | — | 2000-05-02 |
| 6046958 | Latching wordline driver for multi-bank memory | — | 2000-04-04 |
| 6043562 | Digit line architecture for dynamic memory | — | 2000-03-28 |
| 6043542 | Method and integrated circuit structure for preventing latch-up in CMOS integrated circuit devices | Robert Kerr | 2000-03-28 |
| 6041003 | Circuit and method for memory device with defect current isolation | Stephen L. Casper, David L. Pinney | 2000-03-21 |
| 6029250 | Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same | — | 2000-02-22 |
| 6026051 | Low skew differential receiver with disable feature | Russel J. Baker | 2000-02-15 |
| 6018236 | Differential voltage regulator | — | 2000-01-25 |
| 6016282 | Clock vernier adjustment | — | 2000-01-18 |
| 6011732 | Synchronous clock generator including a compound delay-locked loop | Ronnie M. Harrison | 2000-01-04 |
| 6005823 | Memory device with pipelined column address path | Chris G. Martin, Troy A. Manning | 1999-12-21 |
| 5999033 | Low-to-high voltage CMOS driver circuit for driving capacitive loads | William K. Waller | 1999-12-07 |
| 5999480 | Dynamic random-access memory having a hierarchical data path | Adrian E. Ong, Paul S. Zagar, Troy A. Manning, Ken Waller | 1999-12-07 |
| 5981322 | Method for preventing latch-up in cmos integrated circuit devices | Robert Kerr | 1999-11-09 |
| 5970008 | Efficient method for obtaining usable parts from a partially good memory integrated circuit | Paul S. Zagar, Adrian E. Ong | 1999-10-19 |
| 5949254 | Adjustable output driver circuit | — | 1999-09-07 |
| 5946257 | Selective power distribution circuit for an integrated circuit | — | 1999-08-31 |
| 5935263 | Method and apparatus for memory array compressed data testing | Troy A. Manning, Chris G. Martin, Kim Pierce, Wallace E. Fister, Kevin J. Ryan +3 more | 1999-08-10 |
| 5920518 | Synchronous clock generator including delay-locked loop | Ronnie M. Harrison | 1999-07-06 |