JR

Janusz Rajski

MG Mentor Graphics: 79 patents #1 of 698Top 1%
SS Siemens Industry Software: 8 patents #6 of 391Top 2%
CU Carnegie Mellon University: 1 patents #637 of 1,507Top 45%
Nortel Networks Limited: 1 patents #2,518 of 5,294Top 50%
📍 West Linn, OR: #5 of 419 inventorsTop 2%
🗺 Oregon: #124 of 28,073 inventorsTop 1%
Overall (All Time): #8,299 of 4,157,543Top 1%
131
Patents All Time

Issued Patents All Time

Showing 101–125 of 131 patents

Patent #TitleCo-InventorsDate
7478296 Continuous application and decompression of test patterns to a circuit-under-test Mark Kassab, Nilanjan Mukherjee, Jerzy Tyszer 2009-01-13
7437640 Fault diagnosis of compressed test responses having one or more unknown states Grzegorz Mrugalski, Artur Pogiel, Jerzy Tyszer, Chen Wang 2008-10-14
7437636 Method and apparatus for at-speed testing of digital circuits Abu Hassan, Robert L. Thompson, Nagesh Tamarapalli 2008-10-14
7386778 Methods for distributing programs for generating test data Jon Udell, Chen Wang, Mark Kassab 2008-06-10
7370254 Compressing test responses using a compactor Jerzy Tyszer, Chen Wang, Grzegorz Mrugalski, Artur Pogiel 2008-05-06
7302624 Adaptive fault diagnosis of compressed test responses Grzegorz Mrugalski, Artur Pogiel, Jerzy Tyszer, Chen Wang 2007-11-27
7263641 Phase shifter with reduced linear dependency Jerzy Tyszer, Nagesh Tamarapalli 2007-08-28
7260591 Method for synthesizing linear finite state machines Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee 2007-08-21
7239978 Compactor independent fault diagnosis Wu-Tung Cheng, Kun-Han Tsai, Yu Huang, Nagesh Tamarapalli 2007-07-03
7111209 Test pattern compression for an integrated circuit test environment Mark Kassab, Nilanjan Mukherjee, Jerzy Tyszer 2006-09-19
7093175 Decompressor/PRPG for applying pseudo-random and deterministic test patterns Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee 2006-08-15
6966021 Method and apparatus for at-speed testing of digital circuits Abu Hassan, Robert L. Thompson, Nagesh Tamarapalli 2005-11-15
6954888 Arithmetic built-in self-test of multiple scan-based integrated circuits Jerzy Tyszer 2005-10-11
6874109 Phase shifter with reduced linear dependency Jerzy Tyszer, Nagesh Tamarapalli 2005-03-29
6829740 Method and apparatus for selectively compacting test responses Mark Kassab, Nilanjan Mukherjee, Jerzy Tyszer 2004-12-07
6728901 Arithmetic built-in self-test of multiple scan-based integrated circuits Jerzy Tyszer 2004-04-27
6708192 Method for synthesizing linear finite state machines Mark Kassab, Nilanjan Mukherjee, Jerzy Tyszer 2004-03-16
6684358 Decompressor/PRPG for applying pseudo-random and deterministic test patterns Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee 2004-01-27
6662327 Method for clustered test pattern generation 2003-12-09
6557129 Method and apparatus for selectively compacting test responses Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee 2003-04-29
6543020 Test pattern compression for an integrated circuit test environment Mark Kassab, Nilanjan Mukherjee, Jerzy Tyszer 2003-04-01
6539409 Method for synthesizing linear finite state machines Mark Kassab, Nilanjan Mukherjee, Jerzy Tyszer 2003-03-25
6421794 Method and apparatus for diagnosing memory using self-testing circuits John Chen 2002-07-16
6353842 Method for synthesizing linear finite state machines Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee 2002-03-05
6327687 Test pattern compression for an integrated circuit test environment Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee 2001-12-04