JR

Janusz Rajski

MG Mentor Graphics: 79 patents #1 of 698Top 1%
SS Siemens Industry Software: 8 patents #6 of 391Top 2%
CU Carnegie Mellon University: 1 patents #637 of 1,507Top 45%
Nortel Networks Limited: 1 patents #2,518 of 5,294Top 50%
📍 West Linn, OR: #5 of 419 inventorsTop 2%
🗺 Oregon: #124 of 28,073 inventorsTop 1%
Overall (All Time): #8,299 of 4,157,543Top 1%
131
Patents All Time

Issued Patents All Time

Showing 126–131 of 131 patents

Patent #TitleCo-InventorsDate
6070261 Multi-phase test point insertion for built-in self test of integrated circuits Nagesh Tamarapalli 2000-05-30
5991898 Arithmetic built-in self test of multiple scan-based integrated circuits Jerzy Tyszer 1999-11-23
5991909 Parallel decompressor and related methods and apparatuses Jerzy Tyszer 1999-11-23
5737340 Multi-phase test point insertion for built-in self test of integrated circuits Nagesh Tamarapalli 1998-04-07
5528604 Test pattern generation for an electronic circuit using a transformed circuit description Aiman Helmi El-Maleh, Wojciech P. Maly, Thomas E. Marchok 1996-06-18
5313469 Self-testable digital integrator Saman M. I. Adham, Jerzy Tyszer, Mark Kassab 1994-05-17