Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8766454 | Integrated circuit with self-aligned line and via | Yeow Kheng Lim, Randall Cher Liang Cha, Alex See | 2014-07-01 |
| 7721414 | Method of manufacturing 3-D spiral stacked inductor on semiconductor material | Choon-Beng Sia, Kiat Seng Yeo, Shao-fu Sanford Chu, Cheng Yeow Ng, Kok Wai Chew | 2010-05-25 |
| 7119010 | Integrated circuit with self-aligned line and via and manufacturing method therefor | Yeow Kheng Lim, Randall Cher Liang Cha, Alex See | 2006-10-10 |
| 7060573 | Extended poly buffer STI scheme | Victor Lim, Feng Chen, Lap Chan | 2006-06-13 |
| 6998682 | Method of forming a partially depleted silicon on insulator (PDSOI) transistor with a pad lock body extension | Yeen Tat Chan, Kheng Chok Tee, Yiang Aun Nga, Zhao Lun, Diing Shenp Ang | 2006-02-14 |
| 6905919 | Method of forming a partially depleted silicon on insulator (PDSOI) transistor with a pad lock body extension | Yeen Tat Chan, Kheng Chok Tee, Yiang Aun Nga, Zhao Lun, Diing Shenp Ang | 2005-06-14 |
| 6849928 | Dual silicon-on-insulator device wafer die | Randall Cher Liang Cha, Yeow Kheng Lim, Alex See, Tae Jong Lee | 2005-02-01 |
| 6841847 | 3-D spiral stacked inductor on semiconductor material | Choon-Beng Sia, Kiat Seng Yeo, Shao-fu Sanford Chu, Cheng Yeow Ng, Kok Wai Chew | 2005-01-11 |
| 6613648 | Shallow trench isolation using TEOS cap and polysilicon pullback | Seng-Keong Victor Lim, Feng Chen, Kong Hean Lee | 2003-09-02 |
| 6613649 | Method for buffer STI scheme with a hard mask layer as an oxidation barrier | Seng-Keong Victor Lim, Feng Chen, Alex See | 2003-09-02 |
| 6613652 | Method for fabricating SOI devices with option of incorporating air-gap feature for better insulation and performance | Yeow Kheng Lim, Randall Cher Liang Cha, Alex See, Tae Jong Lee | 2003-09-02 |
| 6558994 | Dual silicon-on-insulator device wafer die | Randall Cher Liang Cha, Yeow Kheng Lim, Alex See, Tae Jong Lee | 2003-05-06 |
| 6472697 | Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application | Yeow Kheng Lim, Randall Cher Liang Cha, Alex See, Victor Lim | 2002-10-29 |
| 6468880 | Method for fabricating complementary silicon on insulator devices using wafer bonding | Yeow Kheng Lim, Randall Cher Liang Cha, Alex See, Tae Jong Lee | 2002-10-22 |
| 6403484 | Method to achieve STI planarization | Victor Lim, Lap Chan, James Yong Meng Lee, Chen Feng | 2002-06-11 |
| 6399471 | Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application | Yeow Kheng Lim, Randall Cher Liang Cha, Alex See, Victor Lim | 2002-06-04 |
| 6380084 | Method to form high performance copper damascene interconnects by de-coupling via and metal line filling | Yeow Kheng Lim, Alex See, Cher Liang Cha, Subhash Gupta, Man Siu Tse | 2002-04-30 |
| 6376376 | Method to prevent CU dishing during damascene formation | Victor Lim, Feng Chen | 2002-04-23 |