RR

Richard P. Rouse

Microsoft: 10 patents #4,352 of 40,388Top 15%
AM AMD: 8 patents #1,491 of 9,279Top 20%
CS Cadence Design Systems: 2 patents #781 of 2,263Top 35%
TI Texas Instruments: 2 patents #5,248 of 12,488Top 45%
Overall (All Time): #187,160 of 4,157,543Top 5%
22
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12315834 Electroplated indium bump stacks for cryogenic electronics Christopher CANTALOUBE 2025-05-27
12226746 Reversing bias in polymer synthesis electrode array Bichlien Hoang NGUYEN, Karin Strauss, Gagan Gupta 2025-02-18
12187760 Photon generating substrates for oligonucleotide synthesis Bichlien Hoang NGUYEN, Karin Strauss, Jake SMITH, Douglas Carmean, Matthew David Turner +1 more 2025-01-07
12081278 Transmitting frequency multiplexed signals from a superconducting domain Derek L. Knee, John Murray HORNIBROOK, Ian Douglas Conway Lamb, David J. Reilly 2024-09-03
12064741 Reversing bias in polymer synthesis electrode array Bichlien Hoang NGUYEN, Karin Strauss, Gagan Gupta 2024-08-20
11862593 Electroplated indium bump stacks for cryogenic electronics Christopher CANTALOUBE 2024-01-02
11675222 Magneto-optical modulator-based system for transferring quantum information Foteini KARINOU, Winston Allen SAUNDERS, Haidang Lin, Derek L. Knee, Charles W. Boecker +1 more 2023-06-13
11360140 RF functional probe Seth Kimes, Brandon S. Bohlen 2022-06-14
11114602 Method of forming superconducting layers and traces David B. Tuckerman 2021-09-07
10651362 Method of forming superconducting apparatus including superconducting layers and traces David B. Tuckerman 2020-05-12
8225248 Timing, noise, and power analysis of integrated circuits Haizhou Chen, Li-Fu Chang, Nishath Verghese 2012-07-17
7790561 Gate sidewall spacer and method of manufacture therefor Shashank S. Ekbote, Haowen Bu 2010-09-07
7673260 Modeling device variations in integrated circuit design Haizhou Chen, Li-Fu Chang, Nishath Verghese 2010-03-02
7064043 Wafer bonded MOS decoupling capacitor 2006-06-20
6531347 Method of making recessed source drains to reduce fringing capacitance Carl Robert Huster, Judy Xilin An 2003-03-11
6503801 Non-uniform channel profile via enhanced diffusion Che-Hoo Ng, Judy Xilin An 2003-01-07
6475868 Oxygen implantation for reduction of junction capacitance in MOS transistors Ming-Yin Hao, Asim A. Selcuk, Emi Ishida 2002-11-05
6372582 Indium retrograde channel doping for improved gate oxide reliability Ming-Yin Hao, Emi Ishida, Effiong Ibok 2002-04-16
6306702 Dual spacer method of forming CMOS transistors with substantially the same sub 0.25 micron gate length Ming-Yin Hao, Zicheng Gary Ling 2001-10-23
6242329 Method for manufacturing asymmetric channel transistor Carl Robert Huster, Concetta Riccobene, Donald L. Wollesen 2001-06-05
6225170 Self-aligned damascene gate with contact formation Effiong Ibok 2001-05-01
6080630 Method for forming a MOS device with self-compensating V.sub.T -implants Ognjen Milic-Strkalj, Zoran Krivokapic 2000-06-27