NV

Nishath Verghese

CS Cadence Design Systems: 5 patents #303 of 2,263Top 15%
📍 Sunnyvale, CA: #4,767 of 14,302 inventorsTop 35%
🗺 California: #106,790 of 386,348 inventorsTop 30%
Overall (All Time): #1,018,637 of 4,157,543Top 25%
5
Patents All Time

Issued Patents All Time

Showing 1–5 of 5 patents

Patent #TitleCo-InventorsDate
8225248 Timing, noise, and power analysis of integrated circuits Haizhou Chen, Li-Fu Chang, Richard P. Rouse 2012-07-17
7844438 Method to analyze and correct dynamic power grid variations in ICs Kenneth Tseng 2010-11-30
7673260 Modeling device variations in integrated circuit design Haizhou Chen, Li-Fu Chang, Richard P. Rouse 2010-03-02
7359843 Robust calculation of crosstalk delay change in integrated circuit design Igor Keller, Kenneth Tseng 2008-04-15
7310792 Method and system for modeling variation of circuit parameters in delay calculation for timing analysis Hong Zhao 2007-12-18