KT

Kenneth Tseng

CS Cadence Design Systems: 5 patents #303 of 2,263Top 15%
📍 Cupertino, CA: #2,618 of 6,989 inventorsTop 40%
🗺 California: #106,790 of 386,348 inventorsTop 30%
Overall (All Time): #1,026,413 of 4,157,543Top 25%
5
Patents All Time

Issued Patents All Time

Showing 1–5 of 5 patents

Patent #TitleCo-InventorsDate
7844438 Method to analyze and correct dynamic power grid variations in ICs Nishath Verghese 2010-11-30
7363605 Eliminating false positives in crosstalk noise analysis Alex Kondratyev, Yosinori Watanabe 2008-04-22
7359843 Robust calculation of crosstalk delay change in integrated circuit design Igor Keller, Nishath Verghese 2008-04-15
6990647 Variable stage ratio buffer insertion for noise optimization in a logic network 2006-01-24
6836873 Static noise analysis with noise window estimation and propagation Vinod Kariat 2004-12-28