| 9754071 |
Integrated circuit (IC) design analysis and feature extraction |
Haraprasad Nanjundappa, Basanth Jagannathan, Dureseti Chidambarrao, Christopher V. Baiocco |
2017-09-05 |
| 7890906 |
Method of laying out integrated circuit design based on known polysilicon perimeter densities of individual cells |
James A. Culp, David J. Hathaway, Anthony D. Polson |
2011-02-15 |
| 7877714 |
System and method to optimize semiconductor power by integration of physical design timing and product performance measurements |
Theodoros E. Anemikos, Jeanne P. Spence Bickford, Susan K. Lichtensteiger, Anthony D. Polson |
2011-01-25 |
| 7849433 |
Integrated circuit with uniform polysilicon perimeter density, method and design structure |
James A. Culp, David J. Hathaway, Anthony D. Polson |
2010-12-07 |
| 7810054 |
Method of optimizing power usage of an integrated circuit design by tuning selective voltage binning cut point |
Theodoros E. Anemikos, Jeanne P. Bickford, Susan K. Lichtensteiger, Anthony D. Polson |
2010-10-05 |
| 7805693 |
IC chip design modeling using perimeter density to electrical characteristic correlation |
James A. Culp, Anthony D. Polson |
2010-09-28 |
| 7487487 |
Design structure for monitoring cross chip delay variation on a semiconductor device |
Anthony D. Polson, David E. Lackey, Theodoros E. Anemikos |
2009-02-03 |
| 7237165 |
Method for testing embedded DRAM arrays |
William R. J. Corbin, Jeffrey H. Dreibelbis, Erik A. Nelson, Thomas E. Obremski, Toshiharu Saitoh +1 more |
2007-06-26 |
| 7073100 |
Method for testing embedded DRAM arrays |
William R. J. Corbin, Jeffrey H. Dreibelbis, Erik A. Nelson, Thomas E. Obremski, Toshiharu Saitoh +1 more |
2006-07-04 |
