Issued Patents All Time
Showing 25 most recent of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9256430 | Instruction scheduling approach to improve processor performance | Jens Leenstra, Philipp Panitz, Hans Schlenker | 2016-02-09 |
| 8972961 | Instruction scheduling approach to improve processor performance | Jens Leenstra, Philipp Panitz, Hans Schlenker | 2015-03-03 |
| 8935685 | Instruction scheduling approach to improve processor performance | Jens Leenstra, Philipp Panitz, Hans Schlenker | 2015-01-13 |
| 8762919 | Circuit macro placement using macro aspect ratio based on ports | Joachim Keinert, Thomas Ludwig | 2014-06-24 |
| 8522187 | Method and data processing system to optimize performance of an electric circuit design, data processing program and computer program product | Niels Fricke, Bernd Kemmler, Karsten Muuss, Matthias Ringe | 2013-08-27 |
| 8513663 | Signal repowering chip for 3-dimensional integrated circuit | Markus Buehler, Sebastian Ehrenreich | 2013-08-20 |
| 8418090 | Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool | Jeanne P. Bickford, Jason D. Hibbeler | 2013-04-09 |
| 8234594 | Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same | Brent A. Anderson, Jeanne P. Bickford, Markus Buehler, Jason D. Hibbeler, Edward J. Nowak | 2012-07-31 |
| 8136066 | Apparatus and computer program product for semiconductor yield estimation | Jeanne P. Bickford, Jason D. Hibbeler, William J. Livingstone, Daniel N. Maynard | 2012-03-13 |
| 8132129 | Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool | Jeanne P. Bickford, Jason D. Hibbeler | 2012-03-06 |
| 8056037 | Method for validating logical function and timing behavior of a digital circuit decision | Walter Pietschmann, Juergen Saalmueller, Norbert Schumacher, Volker Urban, Joerg Walter | 2011-11-08 |
| 8015527 | Routing of wires of an electronic circuit | Markus Buehler, Markus Olbrich, Philipp Panitz | 2011-09-06 |
| 8010925 | Method and system for placement of electric circuit components in integrated circuit design | Markus Buehler | 2011-08-30 |
| 8010916 | Test yield estimate for semiconductor products created from a library | Jeanne P. Bickford, Markus Buehler, Jason D. Hibbeler | 2011-08-30 |
| 7996808 | Computer readable medium, system and associated method for designing integrated circuits with loop insertions | Andreas H. A. Arp, Jeanne P. Bickford, Markus Buehler, Philipp Salz | 2011-08-09 |
| 7984394 | Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same | Brent A. Anderson, Jeanne P. Bickford, Markus Buehler, Jason D. Hibbeler, Edward J. Nowak | 2011-07-19 |
| 7962877 | Port assignment in hierarchical designs by abstracting macro logic | Joachim Keinert, Thomas Ludwig | 2011-06-14 |
| 7962881 | Via structure to improve routing of wires within an integrated circuit | Markus Buehler, Ankit Gangwar, Arun Kumar Mishra | 2011-06-14 |
| 7960836 | Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same | Brent A. Anderson, Jeanne P. Bickford, Markus Buehler, Jason D. Hibbeler, Edward J. Nowak | 2011-06-14 |
| 7961932 | Method and apparatus for manufacturing diamond shaped chips | Robert J. Allen, John M. Cohn, Scott Whitney Gould, Peter A. Habitz, Gustavo E. Tellez +2 more | 2011-06-14 |
| 7886245 | Structure for optimizing the signal time behavior of an electronic circuit design | Guenther Hutzl, Stephan Held, Bernhard Korte, Jens Massberg, Matthias Ringe +1 more | 2011-02-08 |
| 7865855 | Method and system for generating a layout for an integrated electronic circuit | Matthias Ringe | 2011-01-04 |
| 7844931 | Method and computer system for optimizing the signal time behavior of an electronic circuit design | Guenther Hutzl, Stephan Held, Bernhard Korte, Jens Massberg, Matthias Ringe +1 more | 2010-11-30 |
| 7755408 | Redundancy in signal distribution trees | Sebastian Ehrenreich, Juergen Pille | 2010-07-13 |
| 7526743 | Method for routing data paths in a semiconductor chip with a plurality of layers | Andreas H. A. Arp, Matthias Ringe | 2009-04-28 |