Issued Patents All Time
Showing 25 most recent of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11650987 | Query response using semantically similar database records | Rajesh Bordawekar | 2023-05-16 |
| 11410031 | Dynamic updating of a word embedding model | Thomas W. Conti, Stephen C. Warren, Rajesh Bordawekar, Christopher Harding | 2022-08-09 |
| 11176301 | Noise impact on function (NIOF) reduction for integrated circuit design | Adam P. Matheny | 2021-11-16 |
| 11030376 | Net routing for integrated circuit (IC) design | Adam P. Matheny | 2021-06-08 |
| 10885243 | Logic partition reporting for integrated circuit design | Adam P. Matheny | 2021-01-05 |
| 10878152 | Single-bit latch optimization for integrated circuit (IC) design | Adam P. Matheny, Alice H. Lee | 2020-12-29 |
| 10831966 | Multi-fanout latch placement optimization for integrated circuit (IC) design | Adam P. Matheny | 2020-11-10 |
| 10831938 | Parallel power down processing of integrated circuit design | Adam P. Matheny | 2020-11-10 |
| 10831953 | Logic partition identifiers for integrated circuit design | Adam P. Matheny | 2020-11-10 |
| 10331840 | Resource aware method for optimizing wires for slew, slack, or noise | Alice H. Lee, Adam P. Matheny | 2019-06-25 |
| 10169526 | Incremental parasitic extraction for coupled timing and power optimization | Kerim Kalafala, Tsz-Mei Ko, Ravichander Ledalla, Alice H. Lee, Adam P. Matheny +1 more | 2019-01-01 |
| 9934341 | Simulation of modifications to microprocessor design | Christopher J. Berry, Chris Aaron Cavitt, Adam P. Matheny, Jesse Peter Surprise, Michael H. Wood | 2018-04-03 |
| 9928322 | Simulation of modifications to microprocessor design | Christopher J. Berry, Chris Aaron Cavitt, Adam P. Matheny, Jesse Peter Surprise, Michael H. Wood | 2018-03-27 |
| 9858383 | Incremental parasitic extraction for coupled timing and power optimization | Kerim Kalafala, Tsz-Mei Ko, Ravichander Ledalla, Alice H. Lee, Adam P. Matheny +1 more | 2018-01-02 |
| 9734270 | Control path power adjustment for chip design | Christopher J. Berry, Kaustav Guha, Haifeng Qian, Sourav Saha | 2017-08-15 |
| 9703910 | Control path power adjustment for chip design | Christopher J. Berry, Kaustav Guha, Haifeng Qian, Sourav Saha | 2017-07-11 |
| 9256705 | Reducing repeater power | Paul D. Kartschoke, Adam P. Matheny | 2016-02-09 |
| 9223918 | Reducing repeater power | Paul D. Kartschoke, Adam P. Matheny | 2015-12-29 |
| 9038009 | Early design cycle optimization | Charles J. Alpert, Robert M. Averill, III, Zhuo Li, Stephen T. Quay | 2015-05-19 |
| 8640075 | Early design cycle optimzation | Charles J. Alpert, Robert M. Averill, III, Zhuo Li, Stephen T. Quay | 2014-01-28 |
| 8108821 | Reduction of logic and delay through latch polarity inversion | Jonathan Y. Chen | 2012-01-31 |
| 8006213 | Optimization method of integrated circuit design for reduction of global clock load and balancing clock skew | Christopher J. Berry, Charlie C. Hwang, David W. Lewis | 2011-08-23 |
| 7979838 | Method of automating creation of a clock control distribution network in an integrated circuit floorplan | Christopher J. Berry, Lawrence D. Curley, Patrick J. Meaney, Travis W. Pouarz, William J. Scarpero, Jr. | 2011-07-12 |
| 7921398 | System and medium for placement which maintain optimized timing behavior, while improving wireability potential | James J. Curtin, Douglas S. Search | 2011-04-05 |
| 7895539 | System for improving a logic circuit and associated methods | Christopher M. Carney, Biagio Pluchino | 2011-02-22 |