Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8001511 | Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies | Trevor J. Bauer, F. Erich Goetting, Bruce E. Talley, Ramakrishna K. Tanikella, Steven P. Young | 2011-08-16 |
| 7451421 | Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies | Trevor J. Bauer, F. Erich Goetting, Bruce E. Talley, Ramakrishna K. Tanikella, Steven P. Young | 2008-11-11 |
| 7249335 | Methods of routing programmable logic devices to minimize programming time | Jay T. Young, Sridhar Krishnamurthy | 2007-07-24 |
| 7149997 | Routing with frame awareness to minimize device programming time and test cost | Jay T. Young, Ian L. McEwen | 2006-12-12 |
| 7143384 | Methods of routing programmable logic devices to minimize programming time | Jay T. Young, Sridhar Krishnamurthy | 2006-11-28 |
| 7107565 | PLD device representation with factored repeatable tiles | Keith R. Bean | 2006-09-12 |
| 7058919 | Methods of generating test designs for testing specific routing resources in programmable logic devices | Jay T. Young, Sridhar Krishnamurthy, Ian L. McEwen | 2006-06-06 |
| 6944809 | Methods of resource optimization in programmable logic devices to reduce test time | Andrew W. Lai, Randy J. Simmons, Teymour M. Mansour, Vincent L. Tong, Jay T. Young +2 more | 2005-09-13 |
| 6907595 | Partial reconfiguration of a programmable logic device using an on-chip processor | Derek R. Curd, Punit S. Kalra, Richard J. LeBlanc, Vincent P. Eck, Stephen W. Trynosky +1 more | 2005-06-14 |
| 6732347 | Clock template for configuring a programmable gate array | Nicolas John Camilleri, Edward S. McGettigan, Kenneth J. Stickney, Jr., Kevin Bixler, Raymond Kong | 2004-05-04 |
| 6553523 | System and method for verifying configuration of a programmable logic device | Chakravarthy K. Allamsetty | 2003-04-22 |
| 6493862 | Method for compressing an FPGA bitsream | Steven P. Young | 2002-12-10 |