Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9105718 | Butted SOI junction isolation structures and devices and method of fabrication | Jeffrey B. Johnson, Shreesh Narasimha, Viorel Ontalus, Robert R. Robison | 2015-08-11 |
| 8754446 | Semiconductor structure having undercut-gate-oxide gate stack enclosed by protective barrier material | Xiaomeng Chen, Shwu-Jen Jeng, Byeong Y. Kim | 2014-06-17 |
| 8741725 | Butted SOI junction isolation structures and devices and method of fabrication | Jeffrey B. Johnson, Shreesh Narasimha, Viorel Ontalus, Robert R. Robison | 2014-06-03 |
| 8642424 | Replacement metal gate structure and methods of manufacture | Sameer H. Jain, Jeffrey B. Johnson, Ying Li, Ravikumar Ramachandran | 2014-02-04 |
| 8482075 | Structure and method for manufacturing asymmetric devices | Andres Bryant, Arvind Kumar, Nivo Rovedo, Robert R. Robison | 2013-07-09 |
| 8232151 | Structure and method for manufacturing asymmetric devices | Andres Bryant, Arvind Kumar, Nivo Rovedo, Robert R. Robison | 2012-07-31 |
| 8084788 | Method of forming source and drain of a field-effect-transistor and structure thereof | Judson R. Holt, Abhishek Dube, Eric C. Harley, Shwu-Jen Jeng, Jeremy J. Kempisty +1 more | 2011-12-27 |
| 8034692 | Structure and method for manufacturing asymmetric devices | Andres Bryant, Arvind Kumar, Nivo Rovedo, Robert R. Robison | 2011-10-11 |
| 8017483 | Method of creating asymmetric field-effect-transistors | Gregory G. Freeman, Shreesh Narasimha, Ning Su, Nivo Rovedo, Werner Rausch +1 more | 2011-09-13 |
| 7659172 | Structure and method for reducing miller capacitance in field effect transistors | Andrew Waite | 2010-02-09 |
| 7491623 | Method of making a semiconductor structure | Xiaomeng Chen, Shwu-Jen Jeng, Byeong Y. Kim | 2009-02-17 |
| 7151023 | Metal gate MOSFET by full semiconductor metal alloy conversion | Mahender Kumar, Sunfei Fang, Jakub Kedzierski, Cyril Cabral, Jr. | 2006-12-19 |